Several fixes to handling of int CC register:

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same
register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7152 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 20 insertions, 16 deletions

diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index ffb45d6413..7cacd65607 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -547,7 +547,7 @@ void PhyRegAlloc::updateInstruction(MachineInstr* MInst, BasicBlock* BB)
         {
           const Value* Val = Op.getVRegValue();
           if (const LiveRange *LR = LRI.getLiveRangeForValue(Val))
-            if (! LR->hasColor())
+            if (LR->isMarkedForSpill())
               insertCode4SpilledLR(LR, MInst, BB, OpNum);
         }
     } // for each operand
@@ -710,10 +710,12 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
   vector<MachineInstr*> MIBef, MIAft;
   vector<MachineInstr*> AdIMid;
   
-  // Choose a register to hold the spilled value.  This may insert code
-  // before and after MInst to free up the value.  If so, this code should
-  // be first and last in the spill sequence before/after MInst.
-  int TmpRegU = getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef, MIAft);
+  // Choose a register to hold the spilled value, if one was not preallocated.
+  // This may insert code before and after MInst to free up the value.  If so,
+  // this code should be first/last in the spill sequence before/after MInst.
+  int TmpRegU=(LR->hasColor()
+               ? MRI.getUnifiedRegNum(LR->getRegClass()->getID(),LR->getColor())
+               : getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
   
   // Set the operand first so that it this register does not get used
   // as a scratch register for later calls to getUsableUniRegAtMI below
@@ -749,7 +751,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
     AdIMid.clear();
   }
   
-  if (isDef) {   // if this is a Def
+  if (isDef || isDefAndUse) {   // if this is a Def
     // for a DEF, we have to store the value produced by this instruction
     // on the stack position allocated for this LR
     
@@ -1125,8 +1127,8 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
 
   for ( ; HMI != HMIEnd ; ++HMI) {
     if (HMI->first && HMI->second) {
-      LiveRange *L = HMI->second;      // get the LiveRange
-      if (!L->hasColor()) {   //  NOTE: ** allocating the size of long Type **
+      LiveRange *L = HMI->second;       // get the LiveRange
+      if (L->isMarkedForSpill()) {      // NOTE: allocating size of long Type **
         int stackOffset = MF.getInfo()->allocateSpilledValue(Type::LongTy);
         L->setSpillOffFromFP(stackOffset);
         if (DEBUG_RA)
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index ffb45d6413..7cacd65607 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -547,7 +547,7 @@ void PhyRegAlloc::updateInstruction(MachineInstr* MInst, BasicBlock* BB)
         {
           const Value* Val = Op.getVRegValue();
           if (const LiveRange *LR = LRI.getLiveRangeForValue(Val))
-            if (! LR->hasColor())
+            if (LR->isMarkedForSpill())
               insertCode4SpilledLR(LR, MInst, BB, OpNum);
         }
     } // for each operand
@@ -710,10 +710,12 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
   vector<MachineInstr*> MIBef, MIAft;
   vector<MachineInstr*> AdIMid;
   
-  // Choose a register to hold the spilled value.  This may insert code
-  // before and after MInst to free up the value.  If so, this code should
-  // be first and last in the spill sequence before/after MInst.
-  int TmpRegU = getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef, MIAft);
+  // Choose a register to hold the spilled value, if one was not preallocated.
+  // This may insert code before and after MInst to free up the value.  If so,
+  // this code should be first/last in the spill sequence before/after MInst.
+  int TmpRegU=(LR->hasColor()
+               ? MRI.getUnifiedRegNum(LR->getRegClass()->getID(),LR->getColor())
+               : getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
   
   // Set the operand first so that it this register does not get used
   // as a scratch register for later calls to getUsableUniRegAtMI below
@@ -749,7 +751,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
     AdIMid.clear();
   }
   
-  if (isDef) {   // if this is a Def
+  if (isDef || isDefAndUse) {   // if this is a Def
     // for a DEF, we have to store the value produced by this instruction
     // on the stack position allocated for this LR
     
@@ -1125,8 +1127,8 @@ void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
 
   for ( ; HMI != HMIEnd ; ++HMI) {
     if (HMI->first && HMI->second) {
-      LiveRange *L = HMI->second;      // get the LiveRange
-      if (!L->hasColor()) {   //  NOTE: ** allocating the size of long Type **
+      LiveRange *L = HMI->second;       // get the LiveRange
+      if (L->isMarkedForSpill()) {      // NOTE: allocating size of long Type **
         int stackOffset = MF.getInfo()->allocateSpilledValue(Type::LongTy);
         L->setSpillOffFromFP(stackOffset);
         if (DEBUG_RA)