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| author | Jim Grosbach <grosbach@apple.com> | 2010-12-15 23:52:36 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-12-15 23:52:36 +0000 |
| commit | 3e333637f172c30adf5c8333b592fbde17ff9f78 (patch) | |
| tree | 61a04c7237ad7936b0b7f31948e6023229fc3f74 /lib | |
| parent | 836c6245ad7e8f2b9f72c2a9e4cb1df101eaf2c7 (diff) | |
| download | llvm-3e333637f172c30adf5c8333b592fbde17ff9f78.tar.gz llvm-3e333637f172c30adf5c8333b592fbde17ff9f78.tar.bz2 llvm-3e333637f172c30adf5c8333b592fbde17ff9f78.tar.xz | |
Thumb1 had two patterns for the same load-from-constant-pool instruction.
Canonicalize on tLDRpci and remove tLDRcp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121920 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMConstantIslandPass.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 13 | ||||
| -rw-r--r-- | lib/Target/ARM/Thumb1RegisterInfo.cpp | 2 |
4 files changed, 2 insertions, 16 deletions
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp index 8066cb735b..126078aae3 100644 --- a/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -615,7 +615,6 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF, break; case ARM::tLDRpci: - case ARM::tLDRcp: Bits = 8; Scale = 4; // +(offset_8*4) break; diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 3e4d72bec1..991814ed11 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -2187,7 +2187,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) { SDValue Pred = getAL(CurDAG); SDValue PredReg = CurDAG->getRegister(0, MVT::i32); SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; - ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, + ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other, Ops, 4); } else { SDValue Ops[] = { diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 58c2034715..2e8b46e853 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -710,19 +710,6 @@ def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, let Inst{7-0} = addr; } -// Special LDR for loads from non-pc-relative constpools. -let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1, - isReMaterializable = 1 in -def tLDRcp : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i, - "ldr", "\t$Rt, $addr", []>, - T1LdStSP<{1,?,?}> { - // A6.2 & A8.6.57 T2 - bits<3> Rt; - bits<8> addr; - let Inst{10-8} = Rt; - let Inst{7-0} = addr; -} - // A8.6.194 & A8.6.192 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, t_addrmode_is4, AddrModeT1_4, diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 41a9cf3bf1..4e77bd87cc 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -63,7 +63,7 @@ void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val); unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); - BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRcp)) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) .addReg(DestReg, getDefRegState(true), SubIdx) .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg); } |