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authorTim Northover <Tim.Northover@arm.com>2013-04-23 06:55:15 +0000
committerTim Northover <Tim.Northover@arm.com>2013-04-23 06:55:15 +0000
commit3e56b43ac8789da3799069bfca456494c07df872 (patch)
tree0b1d85b9635049ea252934a38a39fe81bd18b0e3 /lib
parent2ff97832e593926ea8dbdd5fc5bcf367475638a9 (diff)
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AArch64: remove unnecessary check that RS is valid
AArch64 always demands a register-scavenger, so the pointer should never be NULL. However, in the spirit of paranoia, we'll assert it before use just in case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180080 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/AArch64/AArch64FrameLowering.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp
index dc41f2f605..daa7f1d5ef 100644
--- a/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -367,9 +367,8 @@ AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// shoving a base register and an offset into the instruction then we may well
// need to scavenge registers. We should either specifically add an
// callee-save register for this purpose or allocate an extra spill slot.
-
bool BigStack =
- (RS && MFI->estimateStackSize(MF) >= TII.estimateRSStackLimit(MF))
+ MFI->estimateStackSize(MF) >= TII.estimateRSStackLimit(MF)
|| MFI->hasVarSizedObjects() // Access will be from X29: messes things up
|| (MFI->adjustsStack() && !hasReservedCallFrame(MF));
@@ -392,6 +391,8 @@ AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (ExtraReg != 0) {
MF.getRegInfo().setPhysRegUsed(ExtraReg);
} else {
+ assert(RS && "Expect register scavenger to be available");
+
// Create a stack slot for scavenging purposes. PrologEpilogInserter
// helpfully places it near either SP or FP for us to avoid
// infinitely-regression during scavenging.