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authorChris Lattner <sabre@nondot.org>2010-10-07 00:43:39 +0000
committerChris Lattner <sabre@nondot.org>2010-10-07 00:43:39 +0000
commit511c686f766ba977b667dd04638b68cf241373d5 (patch)
treebc3d054451b4ce6daac3299f259aca8d528cc55a /lib
parent3bbdcea49abddea69d124e7ef055c9fdaa8d12f6 (diff)
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add a new BinOpAI class to represent the immediate form that directly acts on EAX.
This does change the generated .inc files to include the implicit use/def of eax. Since these instructions are only generated by the assembler and disassembler it doesn't actually matter though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115885 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/X86/X86InstrArithmetic.td26
1 files changed, 16 insertions, 10 deletions
diff --git a/lib/Target/X86/X86InstrArithmetic.td b/lib/Target/X86/X86InstrArithmetic.td
index e131538352..9d7629519c 100644
--- a/lib/Target/X86/X86InstrArithmetic.td
+++ b/lib/Target/X86/X86InstrArithmetic.td
@@ -686,6 +686,17 @@ class BinOpMI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
let ImmT = Imm8; // Always 8-bit immediate.
}
+// BinOpAI - Instructions like "add %eax, %eax, imm".
+class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
+ Register areg>
+ : ITy<opcode, RawFrm, typeinfo,
+ (outs), (ins typeinfo.ImmOperand:$src),
+ mnemonic, !strconcat("{$src, %", areg.AsmName, "|%",
+ areg.AsmName, ", $src}"), []> {
+ let ImmT = typeinfo.ImmEncoding;
+ let Uses = [areg];
+ let Defs = [areg];
+}
// Logical operators.
let Defs = [EFLAGS] in {
@@ -737,17 +748,12 @@ def AND64mi32 : BinOpMI<0x80, "and", Xi64, and, MRM4m>;
def AND16mi8 : BinOpMI8<0x82, "and", Xi16, and, MRM4m>;
def AND32mi8 : BinOpMI8<0x82, "and", Xi32, and, MRM4m>;
def AND64mi8 : BinOpMI8<0x82, "and", Xi64, and, MRM4m>;
-
-// FIXME: Implicitly modifies AL.
-def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
- "and{b}\t{$src, %al|%al, $src}", []>;
-def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
- "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
-def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
- "and{l}\t{$src, %eax|%eax, $src}", []>;
-def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
- "and{q}\t{$src, %rax|%rax, $src}", []>;
+def AND8i8 : BinOpAI<0x24, "and", Xi8 , AL>;
+def AND16i16 : BinOpAI<0x24, "and", Xi16, AX>;
+def AND32i32 : BinOpAI<0x24, "and", Xi32, EAX>;
+def AND64i32 : BinOpAI<0x24, "and", Xi64, RAX>;
+
let Constraints = "$src1 = $dst" in {