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| author | Louis Gerbarg <lgg@apple.com> | 2014-04-17 20:51:50 +0000 |
|---|---|---|
| committer | Louis Gerbarg <lgg@apple.com> | 2014-04-17 20:51:50 +0000 |
| commit | 5540570374a374e702bce1c2fa4208ebe9433d74 (patch) | |
| tree | b38874f2f08f19eefc9fe435bb4552a750ab3a9a /lib | |
| parent | 4af58f145d7dececbd866c7f8e942cbfc5801d90 (diff) | |
| download | llvm-5540570374a374e702bce1c2fa4208ebe9433d74.tar.gz llvm-5540570374a374e702bce1c2fa4208ebe9433d74.tar.bz2 llvm-5540570374a374e702bce1c2fa4208ebe9433d74.tar.xz | |
Improve ARM64 vector creation
This patch improves the performance of vector creation in caseiswhere where
several of the lanes in the vector are a constant floating point value. It
also includes new patterns to fold together some of the instructions when the
value is 0.0f. Test cases included.
rdar://16349427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206496 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM64/ARM64ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/ARM64/ARM64InstrInfo.td | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp index 1bb2198c1e..d8ff81104a 100644 --- a/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -4891,7 +4891,7 @@ FailedModImm: if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) isConstant = false; - if (isa<ConstantSDNode>(V)) { + if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) { ++NumConstantLanes; if (!ConstantValue.getNode()) ConstantValue = V; @@ -4955,7 +4955,7 @@ FailedModImm: for (unsigned i = 0; i < NumElts; ++i) { SDValue V = Op.getOperand(i); SDValue LaneIdx = DAG.getConstant(i, MVT::i64); - if (!isa<ConstantSDNode>(V)) { + if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) { // Note that type legalization likely mucked about with the VT of the // source operand, so we may have to convert it here before inserting. Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td index 5bb57c5092..ce15789b54 100644 --- a/lib/Target/ARM64/ARM64InstrInfo.td +++ b/lib/Target/ARM64/ARM64InstrInfo.td @@ -3472,6 +3472,9 @@ def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>; def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>; def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>; +def : Pat<(v2f64 (ARM64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>; +def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>; + // EDIT per word & halfword: 2s, 4h, 4s, & 8h defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">; def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))), |