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authorAkira Hatanaka <ahatanak@gmail.com>2011-09-09 22:11:26 +0000
committerAkira Hatanaka <ahatanak@gmail.com>2011-09-09 22:11:26 +0000
commit588158674572502daefbae5225715070274e6482 (patch)
treed7f5a70aa5faecbb6f9c48f5ce77b3c24de6710e /lib
parentc3ab388ba9574eb93c44ed57ea46acd4f623b5dc (diff)
downloadllvm-588158674572502daefbae5225715070274e6482.tar.gz
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Make F31 and D15 non-reserved registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139420 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/Mips/MipsRegisterInfo.cpp2
-rw-r--r--lib/Target/Mips/MipsRegisterInfo.td4
2 files changed, 1 insertions, 5 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index c12b3560ee..bb06da9ac0 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -129,8 +129,6 @@ getReservedRegs(const MachineFunction &MF) const {
Reserved.set(Mips::SP);
Reserved.set(Mips::FP);
Reserved.set(Mips::RA);
- Reserved.set(Mips::F31);
- Reserved.set(Mips::D15);
return Reserved;
}
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index f0db518b75..9c288e48f5 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -182,9 +182,7 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Not preserved across procedure calls
D2, D3, D4, D5, D8, D9,
// Callee save
- D10, D11, D12, D13, D14,
- // Reserved
- D15)> {
+ D10, D11, D12, D13, D14, D15)> {
let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
}