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authorBruno Cardoso Lopes <bruno.cardoso@gmail.com>2010-07-09 21:46:19 +0000
committerBruno Cardoso Lopes <bruno.cardoso@gmail.com>2010-07-09 21:46:19 +0000
commit58dbf3784d3daff5f1e5e08363aee8290d1a5dc1 (patch)
tree837acac8c5188aea784c672df38d8579613ef0df /lib
parentd52e78efac2da94f9967db343abd46a0fa9cb3b4 (diff)
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Declare YMM subregisters in the right way! Thanks Jakob
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108022 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/X86/X86RegisterInfo.td3
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 7c79efb497..9f0382e3fa 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -181,8 +181,7 @@ let Namespace = "X86" in {
}
// YMM Registers, used by AVX instructions
- // The sub_ss and sub_sd subregs are the same registers with another regclass.
- let CompositeIndices = [(sub_ss), (sub_sd)], SubRegIndices = [sub_xmm] in {
+ let SubRegIndices = [sub_xmm] in {
def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;