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| author | Bill Wendling <isanbard@gmail.com> | 2010-12-16 00:49:54 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2010-12-16 00:49:54 +0000 |
| commit | 5a54516adf2b15fa337445d327ec3ad9bd1e3648 (patch) | |
| tree | 9a994a7c808dfb2504e64c1ba7c31b73ed1fdc4d /lib | |
| parent | dedec2b89dd05891d0e22093887b190462d5b82a (diff) | |
| download | llvm-5a54516adf2b15fa337445d327ec3ad9bd1e3648.tar.gz llvm-5a54516adf2b15fa337445d327ec3ad9bd1e3648.tar.bz2 llvm-5a54516adf2b15fa337445d327ec3ad9bd1e3648.tar.xz | |
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121931 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/Thumb1RegisterInfo.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 4e77bd87cc..9f917234d1 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -356,9 +356,11 @@ static void removeOperands(MachineInstr &MI, unsigned i) { static unsigned convertToNonSPOpcode(unsigned Opcode) { switch (Opcode) { case ARM::tLDRspi: + case ARM::tRestore: // FIXME: Should this opcode be here? return ARM::tLDRi; case ARM::tSTRspi: + case ARM::tSpill: // FIXME: Should this opcode be here? return ARM::tSTRi; } |