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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-06-23 18:00:52 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-06-23 18:00:52 +0000
commit627230239477e2cdf6e74d9fb7523b38341b24f6 (patch)
tree029a8316b32eaa90b79748e6828903fd5b996056 /lib
parent9ad2c7ef924e4e3c782d0c6267ca39e424911df7 (diff)
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R600: Select is not expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211518 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/R600/AMDGPUISelLowering.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp
index 3bde6e1c8f..0cfbf6bcf1 100644
--- a/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -361,6 +361,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setSchedulingPreference(Sched::RegPressure);
setJumpIsExpensive(true);
+ setSelectIsExpensive(false);
+ PredictableSelectIsExpensive = false;
+
// There are no integer divide instructions, and these expand to a pretty
// large sequence of instructions.
setIntDivIsCheap(false);
@@ -383,6 +386,10 @@ MVT AMDGPUTargetLowering::getVectorIdxTy() const {
return MVT::i32;
}
+bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
+ return true;
+}
+
// The backend supports 32 and 64 bit floating point immediates.
// FIXME: Why are we reporting vectors of FP immediates as legal?
bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {