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| author | Brian Gaeke <gaeke@uiuc.edu> | 2003-11-08 18:12:24 +0000 |
|---|---|---|
| committer | Brian Gaeke <gaeke@uiuc.edu> | 2003-11-08 18:12:24 +0000 |
| commit | 641271df3c0d8a9be1480912f4387ad103fb07d0 (patch) | |
| tree | 61c97dd9c8d273ee2fc78830ab2f0b0e52976c07 /lib | |
| parent | 3e2959e2a0f7653147a59f8f98c8e38219824d98 (diff) | |
| download | llvm-641271df3c0d8a9be1480912f4387ad103fb07d0.tar.gz llvm-641271df3c0d8a9be1480912f4387ad103fb07d0.tar.bz2 llvm-641271df3c0d8a9be1480912f4387ad103fb07d0.tar.xz | |
Fix two typos I found in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9806 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/SparcV9/SparcV9RegInfo.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/SparcV9/SparcV9_Reg.td | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index 1a48d9cf20..84dc92e246 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -760,7 +760,7 @@ UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec, RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); #else - // Default to using register g2 for holding large offsets + // Default to using register g4 for holding large offsets OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, SparcIntRegClass::g4); #endif @@ -845,7 +845,7 @@ UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec, RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); #else - // Default to using register g2 for holding large offsets + // Default to using register g4 for holding large offsets OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, SparcIntRegClass::g4); #endif diff --git a/lib/Target/SparcV9/SparcV9_Reg.td b/lib/Target/SparcV9/SparcV9_Reg.td index 40aaac4abe..6d5ad1d55a 100644 --- a/lib/Target/SparcV9/SparcV9_Reg.td +++ b/lib/Target/SparcV9/SparcV9_Reg.td @@ -32,7 +32,7 @@ let Namespace = "SparcV9" in { // For fun, specify a register class. // -// FIXME: the register order should be defined in terms of the prefered +// FIXME: the register order should be defined in terms of the preferred // allocation order... // def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7, |