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authorEvan Cheng <evan.cheng@apple.com>2010-09-21 23:49:07 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-09-21 23:49:07 +0000
commit691e64a54ce899409abe7c131d15ed75e3c1fef5 (patch)
tree2e5a7d62be915c5c6e86a9328d06dd9fbad753b1 /lib
parent882ef2b76a09cdc39d38756fca71cf6cf25ae590 (diff)
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OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMBaseInstrInfo.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 56f911a765..999153188d 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1455,7 +1455,8 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
// Check that CPSR isn't set between the comparison instruction and the one we
// want to change.
- MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
+ MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
+ B = MI->getParent()->begin();
--I;
for (; I != E; --I) {
const MachineInstr &Instr = *I;
@@ -1469,6 +1470,10 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
if (MO.getReg() == ARM::CPSR)
return false;
}
+
+ if (I == B)
+ // The 'and' is below the comparison instruction.
+ return false;
}
// Set the "zero" bit in CPSR.