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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-10-10 23:05:37 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2013-10-10 23:05:37 +0000 |
| commit | 6c066c044ed5b477cdec3eb3e95267783e6ce757 (patch) | |
| tree | 37732fb07eb01c323497278c7489c01f2c875355 /lib | |
| parent | b803d6bf6243644562575fcc04ff3620bd4d77cc (diff) | |
| download | llvm-6c066c044ed5b477cdec3eb3e95267783e6ce757.tar.gz llvm-6c066c044ed5b477cdec3eb3e95267783e6ce757.tar.bz2 llvm-6c066c044ed5b477cdec3eb3e95267783e6ce757.tar.xz | |
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192406 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index fb21f6e860..7cd14d5da6 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -887,8 +887,8 @@ void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, return; } - // This is a conservative aproach, it is possible that we can't determine - // the correct register class and copy too often, but better save than sorry. + // This is a conservative aproach. It is possible that we can't determine the + // correct register class and copy too often, but better safe than sorry. SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32); SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(), Operand.getValueType(), Operand, RC); |