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| author | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-01-29 15:12:02 +0000 |
|---|---|---|
| committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-01-29 15:12:02 +0000 |
| commit | 72d4223ff57f6d03d7802e100cc38634c14c70dc (patch) | |
| tree | 896cea50b6e7a7956ee0ff3bc1c44cf94892dcff /lib | |
| parent | 88390209daa6a501e010624a4328508f9b6ffd24 (diff) | |
| download | llvm-72d4223ff57f6d03d7802e100cc38634c14c70dc.tar.gz llvm-72d4223ff57f6d03d7802e100cc38634c14c70dc.tar.bz2 llvm-72d4223ff57f6d03d7802e100cc38634c14c70dc.tar.xz | |
[mips][msa] Add fill.d instruction.
This instruction is only available on Mips64 cores
that implement the MSA ASE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200400 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrFormats.td | 11 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 6 |
2 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index d463d60354..937898f9d5 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -96,6 +96,17 @@ class MSA_2R_FILL_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_2R_FILL_D_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSA64Inst { + bits<5> rs; + bits<5> wd; + + let Inst{25-18} = major; + let Inst{17-16} = df; + let Inst{15-11} = rs; + let Inst{10-6} = wd; + let Inst{5-0} = minor; +} + class MSA_2R_FMT<bits<8> major, bits<2> df, bits<6> minor>: MSAInst { bits<5> ws; bits<5> wd; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 1da8095f57..1e18af5fc4 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -236,7 +236,7 @@ def vsplati32 : PatFrag<(ops node:$e0), (v4i32 (build_vector node:$e0, node:$e0, node:$e0, node:$e0))>; def vsplati64 : PatFrag<(ops node:$e0), - (v2i64 (build_vector:$v0 node:$e0, node:$e0))>; + (v2i64 (build_vector node:$e0, node:$e0))>; def vsplatf32 : PatFrag<(ops node:$e0), (v4f32 (build_vector node:$e0, node:$e0, node:$e0, node:$e0))>; @@ -730,6 +730,7 @@ class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; +class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; @@ -2093,6 +2094,8 @@ class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, MSA128HOpnd, GPR32Opnd>; class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, MSA128WOpnd, GPR32Opnd>; +class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, + MSA128DOpnd, GPR64Opnd>; class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, FGR32>; @@ -3025,6 +3028,7 @@ def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; def FILL_B : FILL_B_ENC, FILL_B_DESC; def FILL_H : FILL_H_ENC, FILL_H_DESC; def FILL_W : FILL_W_ENC, FILL_W_DESC; +def FILL_D : FILL_D_ENC, FILL_D_DESC; def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; |