summaryrefslogtreecommitdiff
path: root/lib
diff options
context:
space:
mode:
authorBill Wendling <isanbard@gmail.com>2007-02-03 02:41:58 +0000
committerBill Wendling <isanbard@gmail.com>2007-02-03 02:41:58 +0000
commit736610c8741687cb666b5964f45b3ed92d9ef081 (patch)
treed490fe31337c8b9b9ab95ef091e16bfea8d9b9f7 /lib
parente318391d4d3673fbe41e5ef00ce489d85167260b (diff)
downloadllvm-736610c8741687cb666b5964f45b3ed92d9ef081.tar.gz
llvm-736610c8741687cb666b5964f45b3ed92d9ef081.tar.bz2
llvm-736610c8741687cb666b5964f45b3ed92d9ef081.tar.xz
Moved the GetTargetRelocation method from PPCMachOWriter to here. It uses
non-Mach-O-specific information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33819 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/PowerPC/PPCMachOWriterInfo.cpp119
-rw-r--r--lib/Target/PowerPC/PPCMachOWriterInfo.h25
2 files changed, 143 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
index 54e0681222..7b5c4feb33 100644
--- a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
+++ b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
@@ -12,7 +12,10 @@
//===----------------------------------------------------------------------===//
#include "PPCMachOWriterInfo.h"
+#include "PPCRelocations.h"
#include "PPCTargetMachine.h"
+#include "llvm/CodeGen/MachORelocation.h"
+#include "llvm/Support/OutputBuffer.h"
using namespace llvm;
PPCMachOWriterInfo::PPCMachOWriterInfo(const PPCTargetMachine &TM)
@@ -20,3 +23,119 @@ PPCMachOWriterInfo::PPCMachOWriterInfo(const PPCTargetMachine &TM)
HDR_CPU_TYPE_POWERPC64 :
HDR_CPU_TYPE_POWERPC,
HDR_CPU_SUBTYPE_POWERPC_ALL) {}
+PPCMachOWriterInfo::~PPCMachOWriterInfo() {}
+
+
+/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
+/// more PowerPC MachORelocation(s), add the new relocations to the
+/// MachOSection, and rewrite the instruction at the section offset if required
+/// by that relocation type.
+unsigned PPCMachOWriterInfo::GetTargetRelocation(MachineRelocation &MR,
+ unsigned FromIdx,
+ unsigned ToAddr,
+ unsigned ToIdx,
+ OutputBuffer &RelocOut,
+ OutputBuffer &SecOut,
+ bool Scattered) const {
+ unsigned NumRelocs = 0;
+ uint64_t Addr = 0;
+
+ // Keep track of whether or not this is an externally defined relocation.
+ bool isExtern = false;
+
+ // Get the address of whatever it is we're relocating, if possible.
+ if (!isExtern)
+ Addr = (uintptr_t)MR.getResultPointer() + ToAddr;
+
+ switch ((PPC::RelocationType)MR.getRelocationType()) {
+ default: assert(0 && "Unknown PPC relocation type!");
+ case PPC::reloc_absolute_low_ix:
+ assert(0 && "Unhandled PPC relocation type!");
+ break;
+ case PPC::reloc_vanilla:
+ {
+ // FIXME: need to handle 64 bit vanilla relocs
+ MachORelocation VANILLA(MR.getMachineCodeOffset(), ToIdx,
+ false, 2, isExtern,
+ PPC_RELOC_VANILLA,
+ Scattered, (intptr_t)MR.getResultPointer());
+ ++NumRelocs;
+
+ if (Scattered) {
+ RelocOut.outword(VANILLA.getPackedFields());
+ RelocOut.outword(VANILLA.getAddress());
+ } else {
+ RelocOut.outword(VANILLA.getAddress());
+ RelocOut.outword(VANILLA.getPackedFields());
+ }
+
+ intptr_t SymbolOffset;
+
+ if (Scattered)
+ SymbolOffset = Addr + MR.getConstantVal();
+ else
+ SymbolOffset = Addr;
+
+ printf("vanilla fixup: sec_%x[%x] = %x\n", FromIdx,
+ unsigned(MR.getMachineCodeOffset()),
+ unsigned(SymbolOffset));
+ SecOut.fixword(SymbolOffset, MR.getMachineCodeOffset());
+ }
+ break;
+ case PPC::reloc_pcrel_bx:
+ {
+ Addr -= MR.getMachineCodeOffset();
+ Addr >>= 2;
+ Addr &= 0xFFFFFF;
+ Addr <<= 2;
+ Addr |= (SecOut[MR.getMachineCodeOffset()] << 24);
+
+ SecOut.fixword(Addr, MR.getMachineCodeOffset());
+ break;
+ }
+ case PPC::reloc_pcrel_bcx:
+ {
+ Addr -= MR.getMachineCodeOffset();
+ Addr &= 0xFFFC;
+
+ SecOut.fixhalf(Addr, MR.getMachineCodeOffset() + 2);
+ break;
+ }
+ case PPC::reloc_absolute_high:
+ {
+ MachORelocation HA16(MR.getMachineCodeOffset(), ToIdx, false, 2,
+ isExtern, PPC_RELOC_HA16);
+ MachORelocation PAIR(Addr & 0xFFFF, 0xFFFFFF, false, 2, isExtern,
+ PPC_RELOC_PAIR);
+ NumRelocs = 2;
+
+ RelocOut.outword(HA16.getRawAddress());
+ RelocOut.outword(HA16.getPackedFields());
+ RelocOut.outword(PAIR.getRawAddress());
+ RelocOut.outword(PAIR.getPackedFields());
+
+ Addr += 0x8000;
+
+ SecOut.fixhalf(Addr >> 16, MR.getMachineCodeOffset() + 2);
+ break;
+ }
+ case PPC::reloc_absolute_low:
+ {
+ MachORelocation LO16(MR.getMachineCodeOffset(), ToIdx, false, 2,
+ isExtern, PPC_RELOC_LO16);
+ MachORelocation PAIR(Addr >> 16, 0xFFFFFF, false, 2, isExtern,
+ PPC_RELOC_PAIR);
+ NumRelocs = 2;
+
+ RelocOut.outword(LO16.getRawAddress());
+ RelocOut.outword(LO16.getPackedFields());
+ RelocOut.outword(PAIR.getRawAddress());
+ RelocOut.outword(PAIR.getPackedFields());
+
+ SecOut.fixhalf(Addr, MR.getMachineCodeOffset() + 2);
+ break;
+ }
+ }
+
+ return NumRelocs;
+}
diff --git a/lib/Target/PowerPC/PPCMachOWriterInfo.h b/lib/Target/PowerPC/PPCMachOWriterInfo.h
index 1536555949..2cd9efc52a 100644
--- a/lib/Target/PowerPC/PPCMachOWriterInfo.h
+++ b/lib/Target/PowerPC/PPCMachOWriterInfo.h
@@ -19,12 +19,35 @@
namespace llvm {
// Forward declarations
+ class MachineRelocation;
+ class OutputBuffer;
class PPCTargetMachine;
class PPCMachOWriterInfo : public TargetMachOWriterInfo {
public:
PPCMachOWriterInfo(const PPCTargetMachine &TM);
- virtual ~PPCMachOWriterInfo() {}
+ virtual ~PPCMachOWriterInfo();
+
+ virtual unsigned GetTargetRelocation(MachineRelocation &MR,
+ unsigned FromIdx,
+ unsigned ToAddr,
+ unsigned ToIdx,
+ OutputBuffer &RelocOut,
+ OutputBuffer &SecOut,
+ bool Scattered) const;
+
+ // Constants for the relocation r_type field.
+ // See <mach-o/ppc/reloc.h>
+ enum {
+ PPC_RELOC_VANILLA, // generic relocation
+ PPC_RELOC_PAIR, // the second relocation entry of a pair
+ PPC_RELOC_BR14, // 14 bit branch displacement to word address
+ PPC_RELOC_BR24, // 24 bit branch displacement to word address
+ PPC_RELOC_HI16, // a PAIR follows with the low 16 bits
+ PPC_RELOC_LO16, // a PAIR follows with the high 16 bits
+ PPC_RELOC_HA16, // a PAIR follows, which is sign extended to 32b
+ PPC_RELOC_LO14 // LO16 with low 2 bits implicitly zero
+ };
};
} // end llvm namespace