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| author | Evan Cheng <evan.cheng@apple.com> | 2006-06-29 18:04:54 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-06-29 18:04:54 +0000 |
| commit | 775ff18257617da283237b3fe2480f0d8a249ac7 (patch) | |
| tree | f644c7a855d8e8b7586f5bc435e6ce9d22fde18d /lib | |
| parent | 0a41addd7894bc7f7535ffe6a72c9dbe6847f872 (diff) | |
| download | llvm-775ff18257617da283237b3fe2480f0d8a249ac7.tar.gz llvm-775ff18257617da283237b3fe2480f0d8a249ac7.tar.bz2 llvm-775ff18257617da283237b3fe2480f0d8a249ac7.tar.xz | |
Should just use xorps to clear XMM registers for all data types. pxor is also one byte longer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28984 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index f4d3d0e451..4a96c9e82e 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2109,15 +2109,9 @@ def MWAIT : I<0xC9, RawFrm, (ops), "mwait", // Alias instructions that map zero vector to pxor / xorp* for sse. // FIXME: remove when we can teach regalloc that xor reg, reg is ok. -def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst), - "pxor $dst, $dst", - [(set VR128:$dst, (v2i64 immAllZerosV))]>; -def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst), - "xorps $dst, $dst", - [(set VR128:$dst, (v4f32 immAllZerosV))]>; -def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst), - "xorps $dst, $dst", - [(set VR128:$dst, (v2f64 immAllZerosV))]>; +def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst), + "xorps $dst, $dst", + [(set VR128:$dst, (v4f32 immAllZerosV))]>; def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst), "pcmpeqd $dst, $dst", @@ -2265,9 +2259,11 @@ def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; // 128-bit vector all zero's. -def : Pat<(v16i8 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>; -def : Pat<(v8i16 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>; -def : Pat<(v4i32 immAllZerosV), (V_SET0_PI)>, Requires<[HasSSE2]>; +def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>; +def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>; +def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>; +def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>; +def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>; // 128-bit vector all one's. def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>; @@ -2365,10 +2361,10 @@ def : Pat<(v16i8 (vector_shuffle immAllZerosV, // Zeroing a VR128 then do a MOVS{S|D} to the lower bits. def : Pat<(v2f64 (vector_shuffle immAllZerosV, (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)), - (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>; + (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>; def : Pat<(v4f32 (vector_shuffle immAllZerosV, (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)), - (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>; + (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>; } // Splat v2f64 / v2i64 |