diff options
author | Andrew Trick <atrick@apple.com> | 2012-09-18 18:20:00 +0000 |
---|---|---|
committer | Andrew Trick <atrick@apple.com> | 2012-09-18 18:20:00 +0000 |
commit | 781ab4777f683099b919597431022c77854ed415 (patch) | |
tree | 36447dc7435487cb6b1d11533d88b1f3678defdc /lib | |
parent | 37236515cfac7d60a9e1ee6f734618e6939db8c5 (diff) | |
download | llvm-781ab4777f683099b919597431022c77854ed415.tar.gz llvm-781ab4777f683099b919597431022c77854ed415.tar.bz2 llvm-781ab4777f683099b919597431022c77854ed415.tar.xz |
misched: Make ScheduleDAGInstrs use the TargetSchedule interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164153 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 30 |
1 files changed, 14 insertions, 16 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 647fee8017..a1a4efd108 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -52,6 +52,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, DbgValues.clear(); assert(!(IsPostRA && MRI.getNumVirtRegs()) && "Virtual registers must be removed prior to PostRA scheduling"); + + const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); + SchedModel.init(*ST.getSchedModel(), &ST, TII); } /// getUnderlyingObjectFromInt - This is the function that does the work of @@ -274,15 +277,13 @@ void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { // perform its own adjustments. SDep dep(SU, SDep::Data, LDataLatency, *Alias); if (!UnitLatencies) { - unsigned Latency = - TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx, - (UseOp < 0 ? 0 : UseMI), UseOp); - dep.setLatency(Latency); - unsigned MinLatency = - TII->computeOperandLatency(InstrItins, SU->getInstr(), OperIdx, - (UseOp < 0 ? 0 : UseMI), UseOp, - /*FindMin=*/true); - dep.setMinLatency(MinLatency); + MachineInstr *RegUse = UseOp < 0 ? 0 : UseMI; + dep.setLatency( + SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, + RegUse, UseOp, /*FindMin=*/false)); + dep.setMinLatency( + SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, + RegUse, UseOp, /*FindMin=*/true)); ST.adjustSchedDependency(SU, UseSU, dep); } @@ -477,13 +478,10 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) { // Adjust the dependence latency using operand def/use information, then // allow the target to perform its own adjustments. int DefOp = Def->findRegisterDefOperandIdx(Reg); - unsigned Latency = - TII->computeOperandLatency(InstrItins, Def, DefOp, MI, OperIdx); - dep.setLatency(Latency); - unsigned MinLatency = - TII->computeOperandLatency(InstrItins, Def, DefOp, MI, OperIdx, - /*FindMin=*/true); - dep.setMinLatency(MinLatency); + dep.setLatency( + SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, false)); + dep.setMinLatency( + SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx, true)); const TargetSubtargetInfo &ST = TM.getSubtarget<TargetSubtargetInfo>(); ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep)); |