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| author | Tim Northover <tnorthover@apple.com> | 2014-04-30 13:37:02 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-30 13:37:02 +0000 |
| commit | 7870967ba1dbba9cb185c737bc00244ce661abd4 (patch) | |
| tree | 84aaa877f50e10b9d48621ec86211bf1cdff308b /lib | |
| parent | 1636a5f44a04279e0ed80ba7d33f6a1ff1350db9 (diff) | |
| download | llvm-7870967ba1dbba9cb185c737bc00244ce661abd4.tar.gz llvm-7870967ba1dbba9cb185c737bc00244ce661abd4.tar.bz2 llvm-7870967ba1dbba9cb185c737bc00244ce661abd4.tar.xz | |
ARM64: use 32-bit operations for uxtb & uxth
Testing will be enabled shortly with basic-a64-instructions.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207648 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index 6a8310e8f2..ee9c61e528 100644 --- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -4196,9 +4196,8 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, delete Op; } } - // FIXME: Likewise for [su]xt[bh] with a Xd dst operand - else if (NumOperands == 3 && - (Tok == "sxtb" || Tok == "uxtb" || Tok == "sxth" || Tok == "uxth")) { + // FIXME: Likewise for sxt[bh] with a Xd dst operand + else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) { ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]); if (Op->isReg() && ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains( @@ -4214,6 +4213,23 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } } } + // FIXME: Likewise for uxt[bh] with a Xd dst operand + else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) { + ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]); + if (Op->isReg() && + ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains( + Op->getReg())) { + // The source register can be Wn here, but the matcher expects a + // GPR32. Twiddle it here if necessary. + ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]); + if (Op->isReg()) { + unsigned Reg = getWRegFromXReg(Op->getReg()); + Operands[1] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(), + Op->getEndLoc(), getContext()); + delete Op; + } + } + } // Yet another horrible hack to handle FMOV Rd, #0.0 using [WX]ZR. if (NumOperands == 3 && Tok == "fmov") { |