Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph

and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8

22 files changed, 113 insertions, 118 deletions

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
index 1e72b1201b..d0e2fe44b9 100644
--- a/lib/CodeGen/PostRASchedulerList.cpp
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -27,6 +27,7 @@
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Support/Compiler.h"
@@ -78,11 +79,17 @@ namespace {
     /// Topo - A topological ordering for SUnits.
     ScheduleDAGTopologicalSort Topo;
 
+    /// AllocatableSet - The set of allocatable registers.
+    /// We'll be ignoring anti-dependencies on non-allocatable registers,
+    /// because they may not be safe to break.
+    const BitVector AllocatableSet;
+
   public:
-    SchedulePostRATDList(MachineBasicBlock *mbb, const TargetMachine &tm,
+    SchedulePostRATDList(MachineFunction &MF,
                          const MachineLoopInfo &MLI,
                          const MachineDominatorTree &MDT)
-      : ScheduleDAGInstrs(mbb, tm, MLI, MDT), Topo(SUnits) {}
+      : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits),
+        AllocatableSet(TRI->getAllocatableSet(MF)) {}
 
     void Schedule();
 
@@ -100,13 +107,13 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
   const MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
   const MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
 
+  SchedulePostRATDList Scheduler(Fn, MLI, MDT);
+
   // Loop over all of the basic blocks
   for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
        MBB != MBBe; ++MBB) {
 
-    SchedulePostRATDList Scheduler(MBB, Fn.getTarget(), MLI, MDT);
-
-    Scheduler.Run();
+    Scheduler.Run(0, MBB);
 
     Scheduler.EmitSchedule();
   }
@@ -195,10 +202,6 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
   DOUT << "Critical path has total latency "
        << (Max ? Max->getDepth() + Max->Latency : 0) << "\n";
 
-  // We'll be ignoring anti-dependencies on non-allocatable registers, because
-  // they may not be safe to break.
-  const BitVector AllocatableSet = TRI->getAllocatableSet(*MF);
-
   // Track progress along the critical path through the SUnit graph as we walk
   // the instructions.
   SUnit *CriticalPathSU = Max;
@@ -444,8 +447,8 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
     // TODO: Instead of picking the first free register, consider which might
     // be the best.
     if (AntiDepReg != 0) {
-      for (TargetRegisterClass::iterator R = RC->allocation_order_begin(*MF),
-           RE = RC->allocation_order_end(*MF); R != RE; ++R) {
+      for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF),
+           RE = RC->allocation_order_end(MF); R != RE; ++R) {
         unsigned NewReg = *R;
         // Don't replace a register with itself.
         if (NewReg == AntiDepReg) continue;
diff --git a/lib/CodeGen/ScheduleDAG.cpp b/lib/CodeGen/ScheduleDAG.cpp
index 62b816c147..7bad67fde4 100644
--- a/lib/CodeGen/ScheduleDAG.cpp
+++ b/lib/CodeGen/ScheduleDAG.cpp
@@ -21,14 +21,13 @@
 #include <climits>
 using namespace llvm;
 
-ScheduleDAG::ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb,
-                         const TargetMachine &tm)
-  : DAG(dag), BB(bb), TM(tm), MRI(BB->getParent()->getRegInfo()) {
-  TII = TM.getInstrInfo();
-  MF  = BB->getParent();
-  TRI = TM.getRegisterInfo();
-  TLI = TM.getTargetLowering();
-  ConstPool = MF->getConstantPool();
+ScheduleDAG::ScheduleDAG(MachineFunction &mf)
+  : DAG(0), BB(0), TM(mf.getTarget()),
+    TII(TM.getInstrInfo()),
+    TRI(TM.getRegisterInfo()),
+    TLI(TM.getTargetLowering()),
+    MF(mf), MRI(mf.getRegInfo()),
+    ConstPool(MF.getConstantPool()) {
 }
 
 ScheduleDAG::~ScheduleDAG() {}
@@ -46,7 +45,12 @@ void ScheduleDAG::dumpSchedule() const {
 
 /// Run - perform scheduling.
 ///
-void ScheduleDAG::Run() {
+void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
+  SUnits.clear();
+  Sequence.clear();
+  DAG = dag;
+  BB = bb;
+
   Schedule();
   
   DOUT << "*** Final schedule ***\n";
diff --git a/lib/CodeGen/ScheduleDAGEmit.cpp b/lib/CodeGen/ScheduleDAGEmit.cpp
index 1f40771e3b..d5bc67a14f 100644
--- a/lib/CodeGen/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/ScheduleDAGEmit.cpp
@@ -29,7 +29,7 @@
 using namespace llvm;
 
 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
-  MI->addMemOperand(*MF, MO);
+  MI->addMemOperand(MF, MO);
 }
 
 void ScheduleDAG::EmitNoop() {
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index c162d0e3dc..7b5690c07b 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -52,16 +52,18 @@ namespace {
            LE = Header->livein_end(); LI != LE; ++LI)
         LoopLiveIns.insert(*LI);
 
-      VisitRegion(MDT.getNode(Header), Loop, LoopLiveIns);
+      const MachineDomTreeNode *Node = MDT.getNode(Header);
+      const MachineBasicBlock *MBB = Node->getBlock();
+      assert(Loop->contains(MBB) &&
+             "Loop does not contain header!");
+      VisitRegion(Node, MBB, Loop, LoopLiveIns);
     }
 
   private:
     void VisitRegion(const MachineDomTreeNode *Node,
+                     const MachineBasicBlock *MBB,
                      const MachineLoop *Loop,
                      const SmallSet<unsigned, 8> &LoopLiveIns) {
-      MachineBasicBlock *MBB = Node->getBlock();
-      if (!Loop->contains(MBB)) return;
-
       unsigned Count = 0;
       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
            I != E; ++I, ++Count) {
@@ -77,33 +79,28 @@ namespace {
       }
 
       const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
-      for (unsigned I = 0, E = Children.size(); I != E; ++I)
-        VisitRegion(Children[I], Loop, LoopLiveIns);
+      for (std::vector<MachineDomTreeNode*>::const_iterator I =
+           Children.begin(), E = Children.end(); I != E; ++I) {
+        const MachineDomTreeNode *ChildNode = *I;
+        MachineBasicBlock *ChildBlock = ChildNode->getBlock();
+        if (Loop->contains(ChildBlock))
+          VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
+      }
     }
   };
 }
 
-ScheduleDAGInstrs::ScheduleDAGInstrs(MachineBasicBlock *bb,
-                                     const TargetMachine &tm,
+ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
                                      const MachineLoopInfo &mli,
                                      const MachineDominatorTree &mdt)
-  : ScheduleDAG(0, bb, tm), MLI(mli), MDT(mdt) {}
+  : ScheduleDAG(mf), MLI(mli), MDT(mdt) {}
 
 void ScheduleDAGInstrs::BuildSchedGraph() {
-  SUnits.clear();
   SUnits.reserve(BB->size());
 
   // We build scheduling units by walking a block's instruction list from bottom
   // to top.
 
-  // Remember where defs and uses of each physical register are as we procede.
-  std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister] = {};
-  std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister] = {};
-
-  // Remember where unknown loads are after the most recent unknown store
-  // as we procede.
-  std::vector<SUnit *> PendingLoads;
-
   // Remember where a generic side-effecting instruction is as we procede. If
   // ChainMMO is null, this is assumed to have arbitrary side-effects. If
   // ChainMMO is non-null, then Chain makes only a single memory reference.
@@ -378,6 +375,12 @@ void ScheduleDAGInstrs::BuildSchedGraph() {
     if (TID.isTerminator() || MI->isLabel())
       Terminator = SU;
   }
+
+  for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) {
+    Defs[i].clear();
+    Uses[i].clear();
+  }
+  PendingLoads.clear();
 }
 
 void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) {
diff --git a/lib/CodeGen/ScheduleDAGPrinter.cpp b/lib/CodeGen/ScheduleDAGPrinter.cpp
index 2553960457..e2ae5a03c1 100644
--- a/lib/CodeGen/ScheduleDAGPrinter.cpp
+++ b/lib/CodeGen/ScheduleDAGPrinter.cpp
@@ -34,7 +34,7 @@ namespace llvm {
   template<>
   struct DOTGraphTraits<ScheduleDAG*> : public DefaultDOTGraphTraits {
     static std::string getGraphName(const ScheduleDAG *G) {
-      return G->MF->getFunction()->getName();
+      return G->MF.getFunction()->getName();
     }
 
     static bool renderGraphFromBottomUp() {
@@ -83,8 +83,8 @@ std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
 void ScheduleDAG::viewGraph() {
 // This code is only for debugging!
 #ifndef NDEBUG
-  ViewGraph(this, "dag." + MF->getFunction()->getName(),
-            "Scheduling-Units Graph for " + MF->getFunction()->getName() + ':' +
+  ViewGraph(this, "dag." + MF.getFunction()->getName(),
+            "Scheduling-Units Graph for " + MF.getFunction()->getName() + ':' +
             BB->getBasicBlock()->getName());
 #else
   cerr << "ScheduleDAG::viewGraph is only available in debug builds on "
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index f1e43a9024..8b984665be 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -49,7 +49,7 @@ namespace {
 
   class VISIBILITY_HIDDEN DAGCombiner {
     SelectionDAG &DAG;
-    TargetLowering &TLI;
+    const TargetLowering &TLI;
     CombineLevel Level;
     bool LegalOperations;
     bool LegalTypes;
@@ -2836,7 +2836,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
                                     unsigned ExtOpc,
                                     SmallVector<SDNode*, 4> &ExtendNodes,
-                                    TargetLowering &TLI) {
+                                    const TargetLowering &TLI) {
   bool HasCopyToRegUses = false;
   bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
   for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index b86492992c..5154fb1d3e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -14,9 +14,9 @@
 #define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Compiler.h"
@@ -71,9 +71,8 @@ private:
   std::vector<unsigned> LiveRegCycles;
 
 public:
-  ScheduleDAGFast(SelectionDAG *dag, MachineBasicBlock *bb,
-                  const TargetMachine &tm)
-    : ScheduleDAGSDNodes(dag, bb, tm) {}
+  ScheduleDAGFast(MachineFunction &mf)
+    : ScheduleDAGSDNodes(mf) {}
 
   void Schedule();
 
@@ -619,9 +618,6 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
 //                         Public Constructor Functions
 //===----------------------------------------------------------------------===//
 
-llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS,
-                                                SelectionDAG *DAG,
-                                                const TargetMachine *TM,
-                                                MachineBasicBlock *BB, bool) {
-  return new ScheduleDAGFast(DAG, BB, *TM);
+llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS, bool) {
+  return new ScheduleDAGFast(*IS->MF);
 }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 6f0767aa10..2e2cac4121 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -25,7 +25,6 @@
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Compiler.h"
@@ -62,11 +61,10 @@ private:
   HazardRecognizer *HazardRec;
 
 public:
-  ScheduleDAGList(SelectionDAG *dag, MachineBasicBlock *bb,
-                  const TargetMachine &tm,
+  ScheduleDAGList(MachineFunction &mf,
                   SchedulingPriorityQueue *availqueue,
                   HazardRecognizer *HR)
-    : ScheduleDAGSDNodes(dag, bb, tm),
+    : ScheduleDAGSDNodes(mf),
       AvailableQueue(availqueue), HazardRec(HR) {
     }
 
@@ -268,10 +266,8 @@ void ScheduleDAGList::ListScheduleTopDown() {
 /// new hazard recognizer. This scheduler takes ownership of the hazard
 /// recognizer and deletes it when done.
 ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
-                                            SelectionDAG *DAG,
-                                            const TargetMachine *TM,
-                                            MachineBasicBlock *BB, bool Fast) {
-  return new ScheduleDAGList(DAG, BB, *TM,
+                                            bool Fast) {
+  return new ScheduleDAGList(*IS->MF,
                              new LatencyPriorityQueue(),
                              IS->CreateTargetHazardRecognizer());
 }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 03d3ef5fee..bd786daedb 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -18,6 +18,7 @@
 #define DEBUG_TYPE "pre-RA-sched"
 #include "llvm/CodeGen/ScheduleDAGSDNodes.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetMachine.h"
@@ -72,10 +73,10 @@ private:
   ScheduleDAGTopologicalSort Topo;
 
 public:
-  ScheduleDAGRRList(SelectionDAG *dag, MachineBasicBlock *bb,
-                    const TargetMachine &tm, bool isbottomup,
+  ScheduleDAGRRList(MachineFunction &mf,
+                    bool isbottomup,
                     SchedulingPriorityQueue *availqueue)
-    : ScheduleDAGSDNodes(dag, bb, tm), isBottomUp(isbottomup),
+    : ScheduleDAGSDNodes(mf), isBottomUp(isbottomup),
       AvailableQueue(availqueue), Topo(SUnits) {
     }
 
@@ -1346,32 +1347,29 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
 //===----------------------------------------------------------------------===//
 
 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
-                                                    SelectionDAG *DAG,
-                                                    const TargetMachine *TM,
-                                                    MachineBasicBlock *BB,
                                                     bool) {
-  const TargetInstrInfo *TII = TM->getInstrInfo();
-  const TargetRegisterInfo *TRI = TM->getRegisterInfo();
+  const TargetMachine &TM = IS->TM;
+  const TargetInstrInfo *TII = TM.getInstrInfo();
+  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
   
   BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
 
   ScheduleDAGRRList *SD =
-    new ScheduleDAGRRList(DAG, BB, *TM, true, PQ);
+    new ScheduleDAGRRList(*IS->MF, true, PQ);
   PQ->setScheduleDAG(SD);
   return SD;  
 }
 
 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
-                                                    SelectionDAG *DAG,
-                                                    const TargetMachine *TM,
-                                                    MachineBasicBlock *BB,
                                                     bool) {
-  const TargetInstrInfo *TII = TM->getInstrInfo();
-  const TargetRegisterInfo *TRI = TM->getRegisterInfo();
+  const TargetMachine &TM = IS->TM;
+  const TargetInstrInfo *TII = TM.getInstrInfo();
+  const TargetRegisterInfo *TRI = TM.getRegisterInfo();
   
   TDRegReductionPriorityQueue *PQ = new TDRegReductionPriorityQueue(TII, TRI);
 
-  ScheduleDAGRRList *SD = new ScheduleDAGRRList(DAG, BB, *TM, false, PQ);
+  ScheduleDAGRRList *SD =
+    new ScheduleDAGRRList(*IS->MF, false, PQ);
   PQ->setScheduleDAG(SD);
   return SD;
 }
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index c755086a8d..468fd8d4da 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -22,9 +22,8 @@
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
-ScheduleDAGSDNodes::ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
-                                       const TargetMachine &tm)
-  : ScheduleDAG(dag, bb, tm) {
+ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
+  : ScheduleDAG(mf) {
 }
 
 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index e93d4a64f3..282b53363e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -381,7 +381,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 
     // Create the extract_subreg machine instruction.
-    MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
+    MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
 
     // Figure out the register class to create for the destreg.
     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
@@ -427,7 +427,7 @@ void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
     }
     
     // Create the insert_subreg or subreg_to_reg machine instruction.
-    MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
+    MachineInstr *MI = BuildMI(MF, TII->get(Opc));
     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
     
     // If creating a subreg_to_reg, then the first input operand
@@ -484,7 +484,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
 #endif
 
     // Create the new machine instruction.
-    MachineInstr *MI = BuildMI(*MF, II);
+    MachineInstr *MI = BuildMI(MF, II);
     
     // Add result register values for things that are defined by this
     // instruction.
@@ -568,7 +568,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
       --NumOps;  // Ignore the flag operand.
       
     // Create the inline asm machine instruction.
-    MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
+    MachineInstr *MI = BuildMI(MF, TII->get(TargetInstrInfo::INLINEASM));
 
     // Add the asm string as an external symbol operand.
     const char *AsmStr =
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 744ea00ace..e2a4999af6 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -137,19 +137,16 @@ namespace llvm {
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
-                                      SelectionDAG *DAG,
-                                      const TargetMachine *TM,
-                                      MachineBasicBlock *BB,
                                       bool Fast) {
     const TargetLowering &TLI = IS->getTargetLowering();
 
     if (Fast)
-      return createFastDAGScheduler(IS, DAG, TM, BB, Fast);
+      return createFastDAGScheduler(IS, Fast);
     if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
-      return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
+      return createTDListDAGScheduler(IS, Fast);
     assert(TLI.getSchedulingPreference() ==
          TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
-    return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
+    return createBURRListDAGScheduler(IS, Fast);
   }
 }
 
@@ -266,8 +263,8 @@ static void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetLowering &tli, bool fast) :
-  FunctionPass(&ID), TLI(tli),
+SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, bool fast) :
+  FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
   FuncInfo(new FunctionLoweringInfo(TLI)),
   CurDAG(new SelectionDAG(TLI, *FuncInfo)),
   SDL(new SelectionDAGLowering(*CurDAG, TLI, *FuncInfo)),
@@ -304,22 +301,21 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
   AA = &getAnalysis<AliasAnalysis>();
 
   TargetMachine &TM = TLI.getTargetMachine();
-  MachineFunction &MF = MachineFunction::construct(&Fn, TM);
-  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  MF = &MachineFunction::construct(&Fn, TM);
   const TargetInstrInfo &TII = *TM.getInstrInfo();
   const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
 
-  if (MF.getFunction()->hasGC())
-    GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
+  if (MF->getFunction()->hasGC())
+    GFI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF->getFunction());
   else
     GFI = 0;
-  RegInfo = &MF.getRegInfo();
+  RegInfo = &MF->getRegInfo();
   DOUT << "\n\n\n=== " << Fn.getName() << "\n";
 
-  FuncInfo->set(Fn, MF, EnableFastISel);
+  FuncInfo->set(Fn, *MF, EnableFastISel);
   MachineModuleInfo *MMI = getAnalysisToUpdate<MachineModuleInfo>();
   DwarfWriter *DW = getAnalysisToUpdate<DwarfWriter>();
-  CurDAG->init(MF, MMI, DW);
+  CurDAG->init(*MF, MMI, DW);
   SDL->init(GFI, *AA);
 
   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
@@ -327,17 +323,17 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
       // Mark landing pad.
       FuncInfo->MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
 
-  SelectAllBasicBlocks(Fn, MF, MMI, DW, TII);
+  SelectAllBasicBlocks(Fn, *MF, MMI, DW, TII);
 
   // If the first basic block in the function has live ins that need to be
   // copied into vregs, emit the copies into the top of the block before
   // emitting the code for the block.
-  EmitLiveInCopies(MF.begin(), MRI, TRI, TII);
+  EmitLiveInCopies(MF->begin(), *RegInfo, TRI, TII);
 
   // Add function live-ins to entry block live-in set.
   for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
          E = RegInfo->livein_end(); I != E; ++I)
-    MF.begin()->addLiveIn(I->first);
+    MF->begin()->addLiveIn(I->first);
 
 #ifndef NDEBUG
   assert(FuncInfo->CatchInfoFound.size() == FuncInfo->CatchInfoLost.size() &&
@@ -365,7 +361,7 @@ static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
 /// whether object offset >= 0.
 static bool
-IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
+IsFixedFrameObjectWithPosOffset(MachineFrameInfo *MFI, SDValue Op) {
   if (!isa<FrameIndexSDNode>(Op)) return false;
 
   FrameIndexSDNode * FrameIdxNode = dyn_cast<FrameIndexSDNode>(Op);
@@ -380,7 +376,7 @@ IsFixedFrameObjectWithPosOffset(MachineFrameInfo * MFI, SDValue Op) {
 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
 /// virtual registers would be overwritten by direct lowering.
 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
-                                                    MachineFrameInfo * MFI) {
+                                                    MachineFrameInfo *MFI) {
   RegisterSDNode * OpReg = NULL;
   if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
       (Op.getOpcode()== ISD::CopyFromReg &&
@@ -694,14 +690,15 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
   DEBUG(BB->dump());
 }  
 
-void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
+void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn,
+                                            MachineFunction &MF,
                                             MachineModuleInfo *MMI,
                                             DwarfWriter *DW,
                                             const TargetInstrInfo &TII) {
   // Initialize the Fast-ISel state, if needed.
   FastISel *FastIS = 0;
   if (EnableFastISel)
-    FastIS = TLI.createFastISel(*FuncInfo->MF, MMI, DW,
+    FastIS = TLI.createFastISel(MF, MMI, DW,
                                 FuncInfo->ValueMap,
                                 FuncInfo->MBBMap,
                                 FuncInfo->StaticAllocaMap
@@ -1075,9 +1072,8 @@ ScheduleDAG *SelectionDAGISel::Schedule() {
     RegisterScheduler::setDefault(Ctor);
   }
   
-  TargetMachine &TM = getTargetLowering().getTargetMachine();
-  ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
-  Scheduler->Run();
+  ScheduleDAG *Scheduler = Ctor(this, Fast);
+  Scheduler->Run(CurDAG, BB);
 
   return Scheduler;
 }
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 537f6faf78..fcb100ae66 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -46,7 +46,7 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
 
 public:
   explicit ARMDAGToDAGISel(ARMTargetMachine &tm)
-    : SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
+    : SelectionDAGISel(tm), TM(tm),
     Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
   }
 
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 801db44faf..49b52a0de5 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -143,7 +143,7 @@ namespace {
 
   public:
     explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
-      : SelectionDAGISel(*TM.getTargetLowering())
+      : SelectionDAGISel(TM)
     {}
 
     /// getI64Imm - Return a target constant with the specified value, of type
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 1f00bacb5e..858802cbb2 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -227,7 +227,7 @@ class SPUDAGToDAGISel :
 
 public:
   explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
-    SelectionDAGISel(*tm.getTargetLowering()),
+    SelectionDAGISel(tm),
     TM(tm),
     SPUtli(*tm.getTargetLowering())
   {}
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 4532ed2623..cdaa802853 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -38,7 +38,7 @@ namespace {
     unsigned GlobalBaseReg;
   public:
     explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
-      : SelectionDAGISel(*TM.getTargetLowering()) {}
+      : SelectionDAGISel(TM) {}
     
     virtual bool runOnFunction(Function &Fn) {
       // Make sure we re-emit a set of the global base reg if necessary
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 099fb53fae..768ab65892 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -55,7 +55,7 @@ class VISIBILITY_HIDDEN MipsDAGToDAGISel : public SelectionDAGISel {
  
 public:
   explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
-  SelectionDAGISel(*tm.getTargetLowering()),
+  SelectionDAGISel(tm),
   TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
   
   virtual void InstructionSelect();
diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.h b/lib/Target/PIC16/PIC16ISelDAGToDAG.h
index 177313372b..83abed3958 100644
--- a/lib/Target/PIC16/PIC16ISelDAGToDAG.h
+++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.h
@@ -35,7 +35,7 @@ class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
 
 public:
   explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) : 
-        SelectionDAGISel(PIC16Lowering),
+        SelectionDAGISel(tm),
         TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
   
   // Pass Name
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index fdbd126e78..a86604b1aa 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -44,7 +44,7 @@ namespace {
     unsigned GlobalBaseReg;
   public:
     explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
-      : SelectionDAGISel(*tm.getTargetLowering()), TM(tm),
+      : SelectionDAGISel(tm), TM(tm),
         PPCLowering(*TM.getTargetLowering()),
         PPCSubTarget(*TM.getSubtargetImpl()) {}
     
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 34846529b2..12ed94cba6 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -34,7 +34,7 @@ class SparcDAGToDAGISel : public SelectionDAGISel {
   const SparcSubtarget &Subtarget;
 public:
   explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
-    : SelectionDAGISel(*TM.getTargetLowering()),
+    : SelectionDAGISel(TM),
       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
   }
 
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 907aa69206..44c43a2ef8 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -126,7 +126,7 @@ namespace {
 
   public:
     X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
-      : SelectionDAGISel(*tm.getTargetLowering(), fast),
+      : SelectionDAGISel(tm, fast),
         TM(tm), X86Lowering(*TM.getTargetLowering()),
         Subtarget(&TM.getSubtarget<X86Subtarget>()),
         OptForSize(false) {}
diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 684ef0bf12..36d76ef571 100644
--- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -42,7 +42,7 @@ namespace {
 
   public:
     XCoreDAGToDAGISel(XCoreTargetMachine &TM)
-      : SelectionDAGISel(*TM.getTargetLowering()),
+      : SelectionDAGISel(TM),
         Lowering(*TM.getTargetLowering()), 
         Subtarget(*TM.getSubtargetImpl()) { }