diff options
author | Chris Lattner <sabre@nondot.org> | 2006-03-07 06:44:19 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2006-03-07 06:44:19 +0000 |
commit | 7ce64852e8fc260f8a7434217c1b57b85a70a1c8 (patch) | |
tree | 08af672da56edfaa350fd734acf17cc6df1e58ef /lib | |
parent | c6644188208d4aee9a9d6c428710ec1f69837944 (diff) | |
download | llvm-7ce64852e8fc260f8a7434217c1b57b85a70a1c8.tar.gz llvm-7ce64852e8fc260f8a7434217c1b57b85a70a1c8.tar.bz2 llvm-7ce64852e8fc260f8a7434217c1b57b85a70a1c8.tar.xz |
add some comments that describe what we model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26588 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/PowerPC/PPCHazardRecognizers.cpp | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index cd02705fee..1b1559546b 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -22,6 +22,24 @@ using namespace llvm; //===----------------------------------------------------------------------===// // PowerPC 970 Hazard Recognizer // +// This models the dispatch group formation of the PPC970 processor. Dispatch +// groups are bundles of up to five instructions that can contain up to two ALU +// (aka FXU) ops, two FPU ops, two Load/Store ops, one CR op, one VALU op, one +// VPERM op, and one BRANCH op. If the code contains more instructions in a +// sequence than the dispatch group can contain (e.g. three loads in a row) the +// processor terminates the dispatch group early, wasting execution resources. +// +// In addition to these restrictions, there are a number of other restrictions: +// some instructions, e.g. branches, are required to be the last instruction in +// a group. Additionally, only branches can issue in the 5th (last) slot. +// +// Finally, there are a number of "structural" hazards on the PPC970. These +// conditions cause large performance penalties due to misprediction, recovery, +// and replay logic that has to happen. These cases include setting a CTR and +// branching through it in the same dispatch group, and storing to an address, +// then loading from the same address within a dispatch group. To avoid these +// conditions, we insert no-op instructions when appropriate. +// // FIXME: This is missing some significant cases: // 0. Handling of instructions that must be the first/last in a group. // 1. Modeling of microcoded instructions. @@ -30,9 +48,6 @@ using namespace llvm; // 4. Handling of the esoteric cases in "Resource-based Instruction Grouping", // e.g. integer divides that only execute in the second slot. // -// Note: on the PPC970, logical CR operations are more expensive in their three -// address form: ops that read/write the same register are half as expensive as -// void PPCHazardRecognizer970::EndDispatchGroup() { DEBUG(std::cerr << "=== Start of dispatch group\n"); |