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authorEli Friedman <eli.friedman@gmail.com>2011-09-28 21:00:25 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-09-28 21:00:25 +0000
commit7d3e2b78c74ad92bda0836de3e056ee8ec41e446 (patch)
tree8e5f162c3594f789d9a1e3632873fae9bc7e414a /lib
parent32a12ba8c0736a74681563a8f5ec8d81108514b5 (diff)
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PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140723 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index cab9161f5a..fc2d5ce64e 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -8555,6 +8555,13 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
if (Swap)
std::swap(Op0, Op1);
+ // Check that the operation in question is available (most are plain SSE2,
+ // but PCMPGTQ and PCMPEQQ have different requirements).
+ if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX())
+ return SDValue();
+ if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX())
+ return SDValue();
+
// Since SSE has no unsigned integer comparisons, we need to flip the sign
// bits of the inputs before performing those operations.
if (FlipSigns) {