Add some more "get address into register" code and a more TODOs/FIXMEs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 22 insertions, 0 deletions

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 5884da39b4..e08433925f 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -361,10 +361,32 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
   unsigned Reg;
   int Offset;
   
+  // TODO: Think about using loadRegFromStackSlot() here when we can.
+  
   // See if we can handle this as Reg + Offset
   if (!ARMComputeRegOffset(I, Reg, Offset))
     return false;
     
+  // Since the offset may be too large for the load instruction
+  // get the reg+offset into a register.
+  // TODO: Optimize this somewhat.
+  // FIXME: There is more than one register class in the world...
+  unsigned ScratchReg
+    = FuncInfo.MF->getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
+  ARMCC::CondCodes Pred = ARMCC::AL;
+  unsigned PredReg = 0;
+  
+  if (!AFI->isThumbFunction())
+    emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                            ScratchReg, Reg, Offset, Pred, PredReg,
+                            static_cast<const ARMBaseInstrInfo&>(TII));
+  else {
+    assert(AFI->isThumb2Function());
+    emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                           ScratchReg, Reg, Offset, Pred, PredReg,
+                           static_cast<const ARMBaseInstrInfo&>(TII));
+  } 
+    
   unsigned ResultReg = createResultReg(ARM::GPRRegisterClass);
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                           TII.get(ARM::LDR), ResultReg)