Minor postra scheduler cleanup. It could result in more precise antidependence latency on ARM in exceedingly rare cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147594 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 19 insertions, 25 deletions

diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp
index 4418f4023a..71894bde43 100644
--- a/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -260,9 +260,6 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
 
       assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
 
-      std::vector<SUnit *> &UseList = Uses[Reg];
-      // Defs are push in the order they are visited and never reordered.
-      std::vector<SUnit *> &DefList = Defs[Reg];
       // Optionally add output and anti dependencies. For anti
       // dependencies we use a latency of 0 because for a multi-issue
       // target we want to allow the defining instruction to issue
@@ -271,36 +268,33 @@ void ScheduleDAGInstrs::BuildSchedGraph(AliasAnalysis *AA) {
       //       there's no cost for reusing registers.
       SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
       unsigned AOLatency = (Kind == SDep::Anti) ? 0 : 1;
-      for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
-        SUnit *DefSU = DefList[i];
-        if (DefSU == &ExitSU)
-          continue;
-        if (DefSU != SU &&
-            (Kind != SDep::Output || !MO.isDead() ||
-             !DefSU->getInstr()->registerDefIsDead(Reg))) {
-          if (Kind == SDep::Anti)
-            DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/Reg));
-          else {
-            unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j,
-                                                   DefSU->getInstr());
-            DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/Reg));
-          }
-        }
-      }
-      for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
-        std::vector<SUnit *> &MemDefList = Defs[*Alias];
-        for (unsigned i = 0, e = MemDefList.size(); i != e; ++i) {
-          SUnit *DefSU = MemDefList[i];
+      for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) {
+        std::vector<SUnit *> &DefList = Defs[*Alias];
+        for (unsigned i = 0, e = DefList.size(); i != e; ++i) {
+          SUnit *DefSU = DefList[i];
           if (DefSU == &ExitSU)
             continue;
           if (DefSU != SU &&
               (Kind != SDep::Output || !MO.isDead() ||
-               !DefSU->getInstr()->registerDefIsDead(*Alias)))
-            DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias));
+               !DefSU->getInstr()->registerDefIsDead(*Alias))) {
+            if (Kind == SDep::Anti)
+              DefSU->addPred(SDep(SU, Kind, 0, /*Reg=*/*Alias));
+            else {
+              unsigned AOLat = TII->getOutputLatency(InstrItins, MI, j,
+                                                     DefSU->getInstr());
+              DefSU->addPred(SDep(SU, Kind, AOLat, /*Reg=*/*Alias));
+            }
+          }
         }
       }
 
+      // Retrieve the UseList to add data dependencies and update uses.
+      std::vector<SUnit *> &UseList = Uses[Reg];
       if (MO.isDef()) {
+        // Update DefList. Defs are pushed in the order they are visited and
+        // never reordered.
+        std::vector<SUnit *> &DefList = Defs[Reg];
+
         // Add any data dependencies.
         unsigned DataLatency = SU->Latency;
         for (unsigned i = 0, e = UseList.size(); i != e; ++i) {