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author | Tom Stellard <thomas.stellard@amd.com> | 2014-05-09 16:42:16 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-05-09 16:42:16 +0000 |
commit | 87b983680c5718e85ea9545fe34f0ec05e8b016a (patch) | |
tree | 0ef14bda6b14f9f3f9a614d61dd6848328bc8821 /lib | |
parent | bfaccd494f8abcfd5db129235affa7219264bcee (diff) | |
download | llvm-87b983680c5718e85ea9545fe34f0ec05e8b016a.tar.gz llvm-87b983680c5718e85ea9545fe34f0ec05e8b016a.tar.bz2 llvm-87b983680c5718e85ea9545fe34f0ec05e8b016a.tar.xz |
R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208429 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 22 | ||||
-rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.h | 2 | ||||
-rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 12 | ||||
-rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 6 |
4 files changed, 19 insertions, 23 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index f4053802b9..2462de6dd3 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -267,6 +267,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : } setTargetDAGCombine(ISD::MUL); + setTargetDAGCombine(ISD::SELECT_CC); } //===----------------------------------------------------------------------===// @@ -748,16 +749,16 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, } /// \brief Generate Min/Max node -SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op, +SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N, SelectionDAG &DAG) const { - SDLoc DL(Op); - EVT VT = Op.getValueType(); + SDLoc DL(N); + EVT VT = N->getValueType(0); - SDValue LHS = Op.getOperand(0); - SDValue RHS = Op.getOperand(1); - SDValue True = Op.getOperand(2); - SDValue False = Op.getOperand(3); - SDValue CC = Op.getOperand(4); + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + SDValue True = N->getOperand(2); + SDValue False = N->getOperand(3); + SDValue CC = N->getOperand(4); if (VT != MVT::f32 || !((LHS == True && RHS == False) || (LHS == False && RHS == True))) { @@ -804,7 +805,7 @@ SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op, case ISD::SETCC_INVALID: llvm_unreachable("Invalid setcc condcode!"); } - return Op; + return SDValue(); } SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op, @@ -1283,6 +1284,9 @@ SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N, simplifyI24(N1, DCI); return SDValue(); } + case ISD::SELECT_CC: { + return CombineMinMax(N, DAG); + } } return SDValue(); } diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h index 8db476cacf..4a2dad34af 100644 --- a/lib/Target/R600/AMDGPUISelLowering.h +++ b/lib/Target/R600/AMDGPUISelLowering.h @@ -107,7 +107,7 @@ public: SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const; + SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const; const char* getTargetNodeName(unsigned Opcode) const override; virtual SDNode *PostISelFolding(MachineSDNode *N, diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index b40cb6724d..e3bcab02e3 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -986,13 +986,6 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); } - - // Possible Min/Max pattern - SDValue MinMax = LowerMinMax(Op, DAG); - if (MinMax.getNode()) { - return MinMax; - } - // If we make it this for it means we have no native instructions to handle // this SELECT_CC, so we must lower it. SDValue HWTrue, HWFalse; @@ -1672,6 +1665,11 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N, } case ISD::SELECT_CC: { + // Try common optimizations + SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI); + if (Ret.getNode()) + return Ret; + // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq -> // selectcc x, y, a, b, inv(cc) // diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index e688048507..cacff83677 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -902,12 +902,6 @@ SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { EVT VT = Op.getValueType(); SDLoc DL(Op); - // Possible Min/Max pattern - SDValue MinMax = LowerMinMax(Op, DAG); - if (MinMax.getNode()) { - return MinMax; - } - SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); } |