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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-17 23:17:13 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-17 23:17:13 +0000 |
commit | 8936b947760a278b6371335f3411de647989c665 (patch) | |
tree | aee02e757a012bade0d11423022da641af183b3b /lib | |
parent | aad458d57f7ce2969da4d859b1cf705f61cb093e (diff) | |
download | llvm-8936b947760a278b6371335f3411de647989c665.tar.gz llvm-8936b947760a278b6371335f3411de647989c665.tar.bz2 llvm-8936b947760a278b6371335f3411de647989c665.tar.xz |
Zap the last reference to allocation_order_begin().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133310 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index e36e136450..bae3343a85 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -79,9 +79,9 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ - for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), - E = RC->allocation_order_end(MF); I != E; ++I) - R.set(*I); + ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); + for (unsigned i = 0; i != Order.size(); ++i) + R.set(Order[i]); } BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, |