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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-09-29 02:48:41 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-09-29 02:48:41 +0000 |
commit | 8bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868 (patch) | |
tree | d99f34f3f9a620d16ec686d08cd495e8f96b30c6 /lib | |
parent | 5219f86a0bab11dd6895a31653e371e9871a6734 (diff) | |
download | llvm-8bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868.tar.gz llvm-8bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868.tar.bz2 llvm-8bb3d3cb30df06bdcb3ef5a208e3e59f4eeb4868.tar.xz |
Use ExecutionDepsFix instead of NEONMoveFix.
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140772 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 30 | ||||
-rw-r--r-- | lib/Target/ARM/ARMTargetMachine.cpp | 2 |
2 files changed, 21 insertions, 11 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 70ac487e4b..3083097435 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2732,9 +2732,11 @@ ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, // // We use the following execution domain numbering: // -// 0: Generic -// 1: VFP -// 2: NEON +enum ARMExeDomain { + ExeGeneric = 0, + ExeVFP = 1, + ExeNEON = 2 +}; // // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h // @@ -2743,33 +2745,41 @@ ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const { // VMOVD is a VFP instruction, but can be changed to NEON if it isn't // predicated. if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI)) - return std::make_pair(1, 3); + return std::make_pair(ExeVFP, (1<<ExeVFP) | (1<<ExeNEON)); // No other instructions can be swizzled, so just determine their domain. unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask; if (Domain & ARMII::DomainNEON) - return std::make_pair(2, 0); + return std::make_pair(ExeNEON, 0); // Certain instructions can go either way on Cortex-A8. // Treat them as NEON instructions. if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8()) - return std::make_pair(2, 0); + return std::make_pair(ExeNEON, 0); if (Domain & ARMII::DomainVFP) - return std::make_pair(1, 0); + return std::make_pair(ExeVFP, 0); - return std::make_pair(0, 0); + return std::make_pair(ExeGeneric, 0); } void ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const { // We only know how to change VMOVD into VORR. assert(MI->getOpcode() == ARM::VMOVD && "Can only swizzle VMOVD"); - if (Domain != 2) + if (Domain != ExeNEON) return; + // Zap the predicate operands. + assert(!isPredicated(MI) && "Cannot predicate a VORRd"); + MI->RemoveOperand(3); + MI->RemoveOperand(2); + // Change to a VORRd which requires two identical use operands. MI->setDesc(get(ARM::VORRd)); - MachineInstrBuilder(MI).addReg(MI->getOperand(1).getReg()); + + // Add the extra source operand and new predicates. + // This will go before any implicit ops. + AddDefaultPred(MachineInstrBuilder(MI).addReg(MI->getOperand(1).getReg())); } diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index 2cd818abf3..f779ede3e3 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -118,7 +118,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, if (!Subtarget.isThumb1Only()) PM.add(createARMLoadStoreOptimizationPass()); if (Subtarget.hasNEON()) - PM.add(createNEONMoveFixPass()); + PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass)); } // Expand some pseudo instructions into multiple instructions to allow |