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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-04-29 16:37:01 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-04-29 16:37:01 +0000 |
| commit | 8c4dcca434893f4a2e4467a2d4923aeb48ea9476 (patch) | |
| tree | e26f76017c5d53eb5b71e1c8fbfa8ab13b5429f8 /lib | |
| parent | 07f96126af8dc4b6a2081d55ebcca2d113528cf3 (diff) | |
| download | llvm-8c4dcca434893f4a2e4467a2d4923aeb48ea9476.tar.gz llvm-8c4dcca434893f4a2e4467a2d4923aeb48ea9476.tar.bz2 llvm-8c4dcca434893f4a2e4467a2d4923aeb48ea9476.tar.xz | |
[mips] Remove more redundant 'let Predicates = [HasStdEnc]' statements
Summary:
The InstSE class already initializes Predicates to [HasStdEnc].
No functional change (confirmed by diffing tablegen-erated files before and
after)
Differential Revision: http://reviews.llvm.org/D3547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207551 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index b01c08cf50..b7db4883c2 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -364,10 +364,8 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, } /// Floating Point Memory Instructions -let Predicates = [HasStdEnc] in { - def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; - def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; -} +def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; +def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in { def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>; @@ -380,12 +378,10 @@ let Predicates = [NotFP64bit, HasStdEnc] in { } /// Cop2 Memory Instructions -let Predicates = [HasStdEnc] in { - def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>; - def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>; - def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>; - def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>; -} +def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>; +def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>; +def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>; +def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>; // Indexed loads and stores. // Base register + offset register addressing mode (indicated by "x" in the |