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author | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-27 22:01:01 +0000 |
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committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-09-27 22:01:01 +0000 |
commit | 8eea4616bf494647bf76029685c41dfdb8b8caf6 (patch) | |
tree | a576ade3cc24b159c7bc008b58b75272d1274070 /lib | |
parent | d6d9dd647f6194be8da274420aba3fd5014f994f (diff) | |
download | llvm-8eea4616bf494647bf76029685c41dfdb8b8caf6.tar.gz llvm-8eea4616bf494647bf76029685c41dfdb8b8caf6.tar.bz2 llvm-8eea4616bf494647bf76029685c41dfdb8b8caf6.tar.xz |
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
of the instruction definitions using Pat<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140644 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index ca251f797a..2a10a5b859 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -177,10 +177,12 @@ let fd = 0 in { "ctc1\t$fs, $rt", []>; def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs), - "mfc1\t$rt, $fs", []>; + "mfc1\t$rt, $fs", + [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>; def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt), - "mtc1\t$rt, $fs", []>; + "mtc1\t$rt, $fs", + [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; } def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs), @@ -360,9 +362,6 @@ def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>; def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>; def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>; -def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>; -def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>; - let Predicates = [In32BitMode] in { def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>; def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>; |