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author | Craig Topper <craig.topper@gmail.com> | 2011-11-19 17:46:46 +0000 |
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committer | Craig Topper <craig.topper@gmail.com> | 2011-11-19 17:46:46 +0000 |
commit | 98fc72940b8f3ec553c96a719eb0d6f4196fae49 (patch) | |
tree | d2a7ef0b39f839c64b535dbf82ab641528509567 /lib | |
parent | 03300ecaee3ef853669582bcadec34170dbf515f (diff) | |
download | llvm-98fc72940b8f3ec553c96a719eb0d6f4196fae49.tar.gz llvm-98fc72940b8f3ec553c96a719eb0d6f4196fae49.tar.bz2 llvm-98fc72940b8f3ec553c96a719eb0d6f4196fae49.tar.xz |
Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144999 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 17 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 99 |
2 files changed, 42 insertions, 74 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 9585c09ad9..04ec5a1438 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -9515,6 +9515,23 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const case Intrinsic::x86_avx_hsub_pd_256: return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), Op.getOperand(1), Op.getOperand(2)); + case Intrinsic::x86_avx2_psllv_d: + case Intrinsic::x86_avx2_psllv_q: + case Intrinsic::x86_avx2_psllv_d_256: + case Intrinsic::x86_avx2_psllv_q_256: + return DAG.getNode(ISD::SHL, dl, Op.getValueType(), + Op.getOperand(1), Op.getOperand(2)); + case Intrinsic::x86_avx2_psrlv_d: + case Intrinsic::x86_avx2_psrlv_q: + case Intrinsic::x86_avx2_psrlv_d_256: + case Intrinsic::x86_avx2_psrlv_q_256: + return DAG.getNode(ISD::SRL, dl, Op.getValueType(), + Op.getOperand(1), Op.getOperand(2)); + case Intrinsic::x86_avx2_psrav_d: + case Intrinsic::x86_avx2_psrav_d_256: + return DAG.getNode(ISD::SRA, dl, Op.getValueType(), + Op.getOperand(1), Op.getOperand(2)); + // ptest and testp intrinsics. The intrinsic these come from are designed to // return an integer value, not just an instruction so lower it to the ptest // or testp pattern and a setcc for the result. diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index c365fad73e..46ab7138e7 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -7741,111 +7741,62 @@ defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq", //===----------------------------------------------------------------------===// // Variable Bit Shifts // -multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, - Intrinsic Int128, Intrinsic Int256> { +multiclass avx2_var_shift_i32<bits<8> opc, string OpcodeStr, SDNode OpNode> { def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V; + [(set VR128:$dst, + (v4i32 (OpNode VR128:$src1, (v4i32 VR128:$src2))))]>, + VEX_4V; def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR128:$dst, - (Int128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>, - VEX_4V; + (v4i32 (OpNode VR128:$src1, + (bc_v4i32 (memopv2i64 addr:$src2)))))]>, VEX_4V; def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src1, VR256:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V; + [(set VR256:$dst, + (v8i32 (OpNode VR256:$src1, (v8i32 VR256:$src2))))]>, + VEX_4V; def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR256:$dst, - (Int256 VR256:$src1, (bitconvert (memopv4i64 addr:$src2))))]>, - VEX_4V; + (v8i32 (OpNode VR256:$src1, + (bc_v8i32 (memopv4i64 addr:$src2)))))]>, VEX_4V; } -multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr, - Intrinsic Int128, Intrinsic Int256> { +multiclass avx2_var_shift_i64<bits<8> opc, string OpcodeStr, SDNode OpNode> { def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2))]>, VEX_4V; + [(set VR128:$dst, + (v2i64 (OpNode VR128:$src1, (v2i64 VR128:$src2))))]>, + VEX_4V; def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR128:$dst, - (Int128 VR128:$src1, (memopv2i64 addr:$src2)))]>, + (v2i64 (OpNode VR128:$src1, (memopv2i64 addr:$src2))))]>, VEX_4V; def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src1, VR256:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2))]>, VEX_4V; + [(set VR256:$dst, + (v4i64 (OpNode VR256:$src1, (v4i64 VR256:$src2))))]>, + VEX_4V; def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set VR256:$dst, - (Int256 VR256:$src1, (memopv4i64 addr:$src2)))]>, + (v4i64 (OpNode VR256:$src1, (memopv4i64 addr:$src2))))]>, VEX_4V; } -defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", int_x86_avx2_psllv_d, - int_x86_avx2_psllv_d_256>; -defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", int_x86_avx2_psllv_q, - int_x86_avx2_psllv_q_256>, VEX_W; -defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", int_x86_avx2_psrlv_d, - int_x86_avx2_psrlv_d_256>; -defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", int_x86_avx2_psrlv_q, - int_x86_avx2_psrlv_q_256>, VEX_W; -defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", int_x86_avx2_psrav_d, - int_x86_avx2_psrav_d_256>; - -let Predicates = [HasAVX2] in { - def : Pat<(v4i32 (shl (v4i32 VR128:$src1), (v4i32 VR128:$src2))), - (VPSLLVDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (v2i64 VR128:$src2))), - (VPSLLVQrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (srl (v4i32 VR128:$src1), (v4i32 VR128:$src2))), - (VPSRLVDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (v2i64 VR128:$src2))), - (VPSRLVQrr VR128:$src1, VR128:$src2)>; - def : Pat<(v4i32 (sra (v4i32 VR128:$src1), (v4i32 VR128:$src2))), - (VPSRAVDrr VR128:$src1, VR128:$src2)>; - def : Pat<(v8i32 (shl (v8i32 VR256:$src1), (v8i32 VR256:$src2))), - (VPSLLVDYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (v4i64 VR256:$src2))), - (VPSLLVQYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v8i32 (srl (v8i32 VR256:$src1), (v8i32 VR256:$src2))), - (VPSRLVDYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (v4i64 VR256:$src2))), - (VPSRLVQYrr VR256:$src1, VR256:$src2)>; - def : Pat<(v8i32 (sra (v8i32 VR256:$src1), (v8i32 VR256:$src2))), - (VPSRAVDYrr VR256:$src1, VR256:$src2)>; - - def : Pat<(v4i32 (shl (v4i32 VR128:$src1), - (bc_v4i32 (memopv2i64 addr:$src2)))), - (VPSLLVDrm VR128:$src1, addr:$src2)>; - def : Pat<(v2i64 (shl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))), - (VPSLLVQrm VR128:$src1, addr:$src2)>; - def : Pat<(v4i32 (srl (v4i32 VR128:$src1), - (bc_v4i32 (memopv2i64 addr:$src2)))), - (VPSRLVDrm VR128:$src1, addr:$src2)>; - def : Pat<(v2i64 (srl (v2i64 VR128:$src1), (memopv2i64 addr:$src2))), - (VPSRLVQrm VR128:$src1, addr:$src2)>; - def : Pat<(v4i32 (sra (v4i32 VR128:$src1), - (bc_v4i32 (memopv2i64 addr:$src2)))), - (VPSRAVDrm VR128:$src1, addr:$src2)>; - def : Pat<(v8i32 (shl (v8i32 VR256:$src1), - (bc_v8i32 (memopv4i64 addr:$src2)))), - (VPSLLVDYrm VR256:$src1, addr:$src2)>; - def : Pat<(v4i64 (shl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))), - (VPSLLVQYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8i32 (srl (v8i32 VR256:$src1), - (bc_v8i32 (memopv4i64 addr:$src2)))), - (VPSRLVDYrm VR256:$src1, addr:$src2)>; - def : Pat<(v4i64 (srl (v4i64 VR256:$src1), (memopv4i64 addr:$src2))), - (VPSRLVQYrm VR256:$src1, addr:$src2)>; - def : Pat<(v8i32 (sra (v8i32 VR256:$src1), - (bc_v8i32 (memopv4i64 addr:$src2)))), - (VPSRAVDYrm VR256:$src1, addr:$src2)>; -} +defm VPSLLVD : avx2_var_shift_i32<0x47, "vpsllvd", shl>; +defm VPSLLVQ : avx2_var_shift_i64<0x47, "vpsllvq", shl>, VEX_W; +defm VPSRLVD : avx2_var_shift_i32<0x45, "vpsrlvd", srl>; +defm VPSRLVQ : avx2_var_shift_i64<0x45, "vpsrlvq", srl>, VEX_W; +defm VPSRAVD : avx2_var_shift_i32<0x46, "vpsravd", sra>; |