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authorJakob Stoklund Olesen <stoklund@2pi.dk>2013-05-16 18:03:08 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2013-05-16 18:03:08 +0000
commit997fa623fc14122153c58ddda8c90aa30f192cc8 (patch)
treec9417309d692437447d0ce7c29125b5733149b4c /lib
parent347a5079e18278803bc05b197d325b8580e95610 (diff)
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Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/TargetRegisterInfo.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/TargetRegisterInfo.cpp b/lib/CodeGen/TargetRegisterInfo.cpp
index 84b4bfc332..4c21daf07a 100644
--- a/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/lib/CodeGen/TargetRegisterInfo.cpp
@@ -23,10 +23,12 @@ using namespace llvm;
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
regclass_iterator RCB, regclass_iterator RCE,
const char *const *SRINames,
- const unsigned *SRILaneMasks)
+ const unsigned *SRILaneMasks,
+ unsigned SRICoveringLanes)
: InfoDesc(ID), SubRegIndexNames(SRINames),
SubRegIndexLaneMasks(SRILaneMasks),
- RegClassBegin(RCB), RegClassEnd(RCE) {
+ RegClassBegin(RCB), RegClassEnd(RCE),
+ CoveringLanes(SRICoveringLanes) {
}
TargetRegisterInfo::~TargetRegisterInfo() {}