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| author | Evan Cheng <evan.cheng@apple.com> | 2011-09-28 23:16:31 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-09-28 23:16:31 +0000 |
| commit | 9b88d2d7827d19ef05d3f11faf56e4f28aaa7072 (patch) | |
| tree | 7b9a06de22730ef1853cfea61e85254e48c99129 /lib | |
| parent | d42ca4607b840b65141b42788b5fef6c08e22aa6 (diff) | |
| download | llvm-9b88d2d7827d19ef05d3f11faf56e4f28aaa7072.tar.gz llvm-9b88d2d7827d19ef05d3f11faf56e4f28aaa7072.tar.bz2 llvm-9b88d2d7827d19ef05d3f11faf56e4f28aaa7072.tar.xz | |
Tighten a ARM dag combine condition to avoid an identity transformation, which
ends up introducing a cycle in the DAG.
rdar://10196296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 9f313859d5..54f8aaa6d3 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -7344,7 +7344,7 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { // movne r0, y /// FIXME: Turn this into a target neutral optimization? SDValue Res; - if (CC == ARMCC::NE && FalseVal == RHS) { + if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, N->getOperand(3), Cmp); } else if (CC == ARMCC::EQ && TrueVal == RHS) { |