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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-14 18:00:31 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-14 18:00:31 +0000 |
| commit | 9dec507ecb212a7c94659e9b5a9da66cb4b39ea3 (patch) | |
| tree | a6a315db112e29f3229e22836926bc14c4292d37 /lib | |
| parent | eb9a85f09e18b3fe88499710404b38d3a9128f62 (diff) | |
| download | llvm-9dec507ecb212a7c94659e9b5a9da66cb4b39ea3.tar.gz llvm-9dec507ecb212a7c94659e9b5a9da66cb4b39ea3.tar.bz2 llvm-9dec507ecb212a7c94659e9b5a9da66cb4b39ea3.tar.xz | |
ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 2 |
2 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 5d646e7349..7e5d1363dc 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3317,12 +3317,16 @@ def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; // ISB has only full system option -def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>, +def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, + "isb", "\t$opt", []>, Requires<[IsARM, HasDB]> { + bits<4> opt; let Inst{31-4} = 0xf57ff06; - let Inst{3-0} = 0b1111; + let Inst{3-0} = opt; } +def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; + let usesCustomInserter = 1 in { let Uses = [CPSR] in { def ATOMIC_LOAD_ADD_I8 : PseudoInst< diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index fe165b04b4..581d877a20 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -3380,7 +3380,7 @@ static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - if (Opcode == ARM::DMB || Opcode == ARM::DSB) { + if (Opcode == ARM::DMB || Opcode == ARM::DSB || Opcode == ARM::ISB) { // Inst{3-0} encodes the memory barrier option for the variants. unsigned opt = slice(insn, 3, 0); switch (opt) { |