Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147426 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 0 deletions

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 2d9dbd29c0..baf39c270d 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -13133,6 +13133,24 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
       }
   }
 
+  // The VSELECT instruction is lowered to SSE blend instructions. In many cases
+  // the mask is sign-extended to fill the entire lane. However, we only care
+  // for the highest bit. Convert sign_extend to srl because it is cheaper.
+  // (vselect(sign_extend(x))) ->  vselect(srl(x))
+  if (N->getOpcode() == ISD::VSELECT &&
+      Cond.getOpcode() == ISD::SIGN_EXTEND_INREG && Cond.hasOneUse()) {
+    EVT CondVT = Cond.getValueType();
+    EVT SExtTy = cast<VTSDNode>(Cond.getOperand(1))->getVT();
+    unsigned BitsDiff = CondVT.getScalarType().getSizeInBits() -
+                        SExtTy.getScalarType().getSizeInBits();
+
+    EVT ShiftType = EVT::getVectorVT(*DAG.getContext(),
+                MVT::i32, CondVT.getVectorNumElements());
+    SDValue SHL = DAG.getNode(ISD::SHL, DL, CondVT, Cond.getOperand(0),
+                DAG.getConstant(BitsDiff, ShiftType));
+    return DAG.getNode(ISD::VSELECT, DL, VT, SHL, LHS, RHS);
+  }
+
   return SDValue();
 }