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author | Quentin Colombet <qcolombet@apple.com> | 2014-03-12 17:33:42 +0000 |
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committer | Quentin Colombet <qcolombet@apple.com> | 2014-03-12 17:33:42 +0000 |
commit | a6b6d52299ad2bfe34aa4949e64f964bc9c1abc9 (patch) | |
tree | d9e382e233ba0ee003b95ebf18179b2dac12ba05 /lib | |
parent | 097963a442609b1d5dff6ea30256458a2a618207 (diff) | |
download | llvm-a6b6d52299ad2bfe34aa4949e64f964bc9c1abc9.tar.gz llvm-a6b6d52299ad2bfe34aa4949e64f964bc9c1abc9.tar.bz2 llvm-a6b6d52299ad2bfe34aa4949e64f964bc9c1abc9.tar.xz |
[X86] Set the scheduling resources of some of the FPStack instructions.
This is related to <rdar://problem/15607571>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203682 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86InstrFPStack.td | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td index 1ff818c5c3..4ad7b7e32a 100644 --- a/lib/Target/X86/X86InstrFPStack.td +++ b/lib/Target/X86/X86InstrFPStack.td @@ -206,17 +206,26 @@ def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src), } let Defs = [FPSW] in { +// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling +// resources. defm ADD : FPBinary_rr<fadd>; defm SUB : FPBinary_rr<fsub>; defm MUL : FPBinary_rr<fmul>; defm DIV : FPBinary_rr<fdiv>; +// Sets the scheduling resources for the actual NAME#_F<size>m defintions. +let SchedRW = [WriteFAddLd] in { defm ADD : FPBinary<fadd, MRM0m, "add">; defm SUB : FPBinary<fsub, MRM4m, "sub">; defm SUBR: FPBinary<fsub ,MRM5m, "subr">; +} +let SchedRW = [WriteFMulLd] in { defm MUL : FPBinary<fmul, MRM1m, "mul">; +} +let SchedRW = [WriteFDivLd] in { defm DIV : FPBinary<fdiv, MRM6m, "div">; defm DIVR: FPBinary<fdiv, MRM7m, "divr">; } +} class FPST0rInst<Format fp, string asm> : FPI<0xD8, fp, (outs), (ins RST:$op), asm>; @@ -228,6 +237,7 @@ class FPrST0PInst<Format fp, string asm> // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion // of some of the 'reverse' forms of the fsub and fdiv instructions. As such, // we have to put some 'r's in and take them out of weird places. +let SchedRW = [WriteFAdd] in { def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t$op">; def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st(0), $op|$op, st(0)}">; def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t$op">; @@ -237,15 +247,20 @@ def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">; def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">; def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">; def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">; +} // SchedRW +let SchedRW = [WriteFMul] in { def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">; def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">; def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">; +} // SchedRW +let SchedRW = [WriteFDiv] in { def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t$op">; def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st(0), $op|$op, st(0)}">; def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t$op">; def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t$op">; def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st(0), $op|$op, st(0)}">; def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t$op">; +} // SchedRW def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">; def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">; @@ -264,7 +279,9 @@ def _F : FPI<0xD9, fp, (outs), (ins), asmstring>; let Defs = [FPSW] in { defm CHS : FPUnary<fneg, MRM_E0, "fchs">; defm ABS : FPUnary<fabs, MRM_E1, "fabs">; +let SchedRW = [WriteFSqrt] in { defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">; +} defm SIN : FPUnary<fsin, MRM_FE, "fsin">; defm COS : FPUnary<fcos, MRM_FF, "fcos">; |