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author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-28 10:44:47 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-28 10:44:47 +0000 |
commit | abbcf3bd47ad8ffa70f48ebd924f99fff5c22131 (patch) | |
tree | eb840843c5b3d6dd8f3b31e86fbf1bd2f2e49796 /lib | |
parent | 477168192c98e1f75a5bc6db3d34a177f327bd34 (diff) | |
download | llvm-abbcf3bd47ad8ffa70f48ebd924f99fff5c22131.tar.gz llvm-abbcf3bd47ad8ffa70f48ebd924f99fff5c22131.tar.bz2 llvm-abbcf3bd47ad8ffa70f48ebd924f99fff5c22131.tar.xz |
[mips][msa] Added move.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189471 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 12 | ||||
-rw-r--r-- | lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 16 |
2 files changed, 28 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index e53b29ec65..eb95c7878a 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -542,6 +542,8 @@ class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; +class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; + class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; @@ -1852,6 +1854,14 @@ class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", int_mips_mod_u_w, NoItinerary, class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", int_mips_mod_u_d, NoItinerary, MSA128D, MSA128D>; +class MOVE_V_DESC { + dag OutOperandList = (outs MSA128B:$wd); + dag InOperandList = (ins MSA128B:$ws); + string AsmString = "move.v\t$wd, $ws"; + list<dag> Pattern = []; + InstrItinClass Itinerary = NoItinerary; +} + class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, NoItinerary, MSA128H, MSA128H>; class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, @@ -2689,6 +2699,8 @@ def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC, Requires<[HasMSA]>; def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC, Requires<[HasMSA]>; def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC, Requires<[HasMSA]>; +def MOVE_V : MOVE_V_ENC, MOVE_V_DESC, Requires<[HasMSA]>; + def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC, Requires<[HasMSA]>; def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC, Requires<[HasMSA]>; diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 221aedacd3..27fcaa3391 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -463,6 +463,22 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) { break; } + case ISD::INTRINSIC_WO_CHAIN: { + switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) { + default: + break; + + case Intrinsic::mips_move_v: + // Like an assignment but will always produce a move.v even if + // unnecessary. + return std::make_pair(true, + CurDAG->getMachineNode(Mips::MOVE_V, DL, + Node->getValueType(0), + Node->getOperand(1))); + } + break; + } + case ISD::INTRINSIC_VOID: { switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { default: |