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authorAdam Nemet <anemet@apple.com>2014-05-20 21:47:07 +0000
committerAdam Nemet <anemet@apple.com>2014-05-20 21:47:07 +0000
commitadf1668bec523d96a6ddc9fffcc7ae092e919197 (patch)
treec3a26324b05524018c4095444cce7c3ea80634a6 /lib
parente94103adcde704725ccfcd1481035bbc301f755a (diff)
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[ARM64] PR19792: Fix cycle in DAG after performPostLD1Combine
Povray and dealII currently assert with "Overran sorted position" in AssignTopologicalOrder. The problem is that performPostLD1Combine can introduce cycles. Consider: (insert_vector_elt (INSERT_SUBREG undef, (load (add %vreg0, Constant<8>), undef), <= A TargetConstant<2>), (load %vreg0, undef), <= B Constant<1>) This is turned into a LD1LANEpost node. However the address in A is not a valid user of the post-incremented address of B in LD1LANEpost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209242 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM64/ARM64ISelLowering.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp
index 538360cf39..385373116d 100644
--- a/lib/Target/ARM64/ARM64ISelLowering.cpp
+++ b/lib/Target/ARM64/ARM64ISelLowering.cpp
@@ -7298,6 +7298,7 @@ static SDValue performPostLD1Combine(SDNode *N,
}
SDValue Addr = LD->getOperand(1);
+ SDValue Vector = N->getOperand(0);
// Search for a use of the address operand that is an increment.
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
Addr.getNode()->use_end(); UI != UE; ++UI) {
@@ -7310,6 +7311,10 @@ static SDValue performPostLD1Combine(SDNode *N,
// would create a cycle.
if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
continue;
+ // Also check that add is not used in the vector operand. This would also
+ // create a cycle.
+ if (User->isPredecessorOf(Vector.getNode()))
+ continue;
// If the increment is a constant, it must match the memory ref size.
SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
@@ -7324,7 +7329,7 @@ static SDValue performPostLD1Combine(SDNode *N,
SmallVector<SDValue, 8> Ops;
Ops.push_back(LD->getOperand(0)); // Chain
if (IsLaneOp) {
- Ops.push_back(N->getOperand(0)); // The vector to be inserted
+ Ops.push_back(Vector); // The vector to be inserted
Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
}
Ops.push_back(Addr);