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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:44:26 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:44:26 +0000 |
| commit | ae30bea9d74446ec9cc30fe3f639c1431d51bb9b (patch) | |
| tree | 8b101590dd087bffce49abe9d62b7b7dcd9282fb /lib | |
| parent | 7face7587821218b2b3cc0579315bea056cc8e66 (diff) | |
| download | llvm-ae30bea9d74446ec9cc30fe3f639c1431d51bb9b.tar.gz llvm-ae30bea9d74446ec9cc30fe3f639c1431d51bb9b.tar.bz2 llvm-ae30bea9d74446ec9cc30fe3f639c1431d51bb9b.tar.xz | |
[ARM64] Add missing shifted register MVN alias to ORN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205891 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM64/ARM64InstrInfo.td | 5 | ||||
| -rw-r--r-- | lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp | 8 |
2 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td index 241ada9ca2..ca0ff68178 100644 --- a/lib/Target/ARM64/ARM64InstrInfo.td +++ b/lib/Target/ARM64/ARM64InstrInfo.td @@ -624,6 +624,11 @@ def : InstAlias<"mvn $Wd, $Wm", def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>; +def : InstAlias<"mvn $Wd, $Wm, $sh", + (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>; +def : InstAlias<"mvn $Xd, $Xm, $sh", + (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>; + def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>; def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>; diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp index 749cb5232e..a10624a0f8 100644 --- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp +++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp @@ -191,6 +191,14 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, return; } + // ORN Wn, WZR, Wm{, lshift #imm} ==> MVN Wn, Wm{, lshift #imm} + // ORN Xn, XZR, Xm{, lshift #imm} ==> MVN Xn, Xm{, lshift #imm} + if ((Opcode == ARM64::ORNWrs && MI->getOperand(1).getReg() == ARM64::WZR) || + (Opcode == ARM64::ORNXrs && MI->getOperand(1).getReg() == ARM64::XZR)) { + O << "\tmvn\t" << getRegisterName(MI->getOperand(0).getReg()) << ", "; + printShiftedRegister(MI, 2, O); + return; + } // SUBS WZR, Wn, #imm ==> CMP Wn, #imm // SUBS XZR, Xn, #imm ==> CMP Xn, #imm if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) || |