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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-03-21 15:51:53 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-03-21 15:51:53 +0000 |
| commit | af4c7da3064af741c27d528ba36a9cdbebd4a58a (patch) | |
| tree | 7d6fa47b25f846ced7881d77ce3a75acea706f4a /lib | |
| parent | 1b05bb2900d8bb69818ab13e0851a5b43642d2c7 (diff) | |
| download | llvm-af4c7da3064af741c27d528ba36a9cdbebd4a58a.tar.gz llvm-af4c7da3064af741c27d528ba36a9cdbebd4a58a.tar.bz2 llvm-af4c7da3064af741c27d528ba36a9cdbebd4a58a.tar.xz | |
R600/SI: Use SGPR_(32|64) reg clases when lowering SI_ADDR64_RSRC
The SReg_(32|64) register classes contain special registers in addition
to the numbered SGPRs. This can lead to machine verifier errors when
these register classes are used as sub-registers for SReg_128, since
SReg_128 only uses the numbered SGPRs.
Replacing SReg_(32|64) with SGPR_(32|64) fixes this problem, since
the SGPR_(32|64) register classes contain only numbered SGPRs.
Tests cases for this are comming in a later commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204474 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/SIISelLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp index 8cf1b82b7b..52e5a16759 100644 --- a/lib/Target/R600/SIISelLowering.cpp +++ b/lib/Target/R600/SIISelLowering.cpp @@ -398,10 +398,10 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo()); MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); unsigned SuperReg = MI->getOperand(0).getReg(); - unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); - unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); - unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); - unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); + unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass); + unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass); + unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); + unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo) .addOperand(MI->getOperand(1)); BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo) |