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| author | Dan Gohman <gohman@apple.com> | 2008-07-28 22:18:25 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-07-28 22:18:25 +0000 |
| commit | b1e8cad61e64dd7f56b0c62b53f9c1fc86d599f7 (patch) | |
| tree | faaed90dd3b7d23f7a990f7846bb2d79263ec383 /lib | |
| parent | fed90b6d097d50881afb45e4d79f430db66dd741 (diff) | |
| download | llvm-b1e8cad61e64dd7f56b0c62b53f9c1fc86d599f7.tar.gz llvm-b1e8cad61e64dd7f56b0c62b53f9c1fc86d599f7.tar.bz2 llvm-b1e8cad61e64dd7f56b0c62b53f9c1fc86d599f7.tar.xz | |
Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 10 |
2 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 23a403068b..932e1b7afc 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -1240,6 +1240,12 @@ def : Pat<(and GR64:$src, i64immFFFFFFFF), (SUBREG_TO_REG (i64 0), (i32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)), x86_subreg_32bit)>; +// r & (2^16-1) ==> movz +def : Pat<(and GR64:$src, 0xffff), + (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>; +// r & (2^8-1) ==> movz +def : Pat<(and GR64:$src, 0xff), + (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>; // (shl x, 1) ==> (add x, x) def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 4f3a3af0f9..9996195407 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2763,6 +2763,16 @@ def : Pat<(i32 (and (loadi32 addr:$src), (i32 65535))),(MOVZX32rm16 addr:$src)>; // Some peepholes //===----------------------------------------------------------------------===// +// r & (2^16-1) ==> movz +def : Pat<(and GR32:$src1, 0xffff), + (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit)))>; +// r & (2^8-1) ==> movz +def : Pat<(and GR32:$src1, 0xff), + (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit)))>; +// r & (2^8-1) ==> movz +def : Pat<(and GR16:$src1, 0xff), + (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>; + // (shl x, 1) ==> (add x, x) def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>; def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>; |