diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-02-02 00:05:35 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-02-02 00:05:35 +0000 |
| commit | b2abb9752eaba1395b5b6773fbf645036eb992f2 (patch) | |
| tree | 698fdb39539e3c8775dca90288f7502e185fa054 /lib | |
| parent | eb97c0499bda650d84bba2079d4007a4d3ec0246 (diff) | |
| download | llvm-b2abb9752eaba1395b5b6773fbf645036eb992f2.tar.gz llvm-b2abb9752eaba1395b5b6773fbf645036eb992f2.tar.bz2 llvm-b2abb9752eaba1395b5b6773fbf645036eb992f2.tar.xz | |
R600/SI: Fix insertelement with dynamic indices.
This didn't work for any integer vectors, and didn't
work with some sizes of float vectors. This should now
work with all sizes of float and i32 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200619 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/SIInstructions.td | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 912b59a9e7..a5a0dbb711 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1671,8 +1671,13 @@ def : BitConvert <i128, v4i32, VReg_128>; def : BitConvert <v8i32, v32i8, SReg_256>; def : BitConvert <v32i8, v8i32, SReg_256>; def : BitConvert <v8i32, v32i8, VReg_256>; +def : BitConvert <v8i32, v8f32, VReg_256>; +def : BitConvert <v8f32, v8i32, VReg_256>; def : BitConvert <v32i8, v8i32, VReg_256>; +def : BitConvert <v16i32, v16f32, VReg_512>; +def : BitConvert <v16f32, v16i32, VReg_512>; + /********** =================== **********/ /********** Src & Dst modifiers **********/ /********** =================== **********/ @@ -2064,7 +2069,7 @@ def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; /********** Indirect adressing **********/ /********** ====================== **********/ -multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { +multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> { // 1. Extract with offset def : Pat< @@ -2080,21 +2085,26 @@ multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { // 3. Insert with offset def : Pat< - (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), + (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)), (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) >; // 4. Insert without offset def : Pat< - (vector_insert vt:$vec, f32:$val, i32:$idx), + (vector_insert vt:$vec, eltvt:$val, i32:$idx), (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) >; } -defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; -defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; -defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; -defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; +defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>; +defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>; +defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>; +defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>; + +defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>; +defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>; +defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>; +defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>; /********** =============== **********/ /********** Conditions **********/ |