diff options
| author | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-21 20:11:47 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2013-10-21 20:11:47 +0000 |
| commit | b5eae81267649a7ce53debe8196533f7a0472f5b (patch) | |
| tree | 323b19b47cda31ed60d60e872b1c78ceeab112f1 /lib | |
| parent | f2089e1dd810236f716c1a45fa1e561dce5074e8 (diff) | |
| download | llvm-b5eae81267649a7ce53debe8196533f7a0472f5b.tar.gz llvm-b5eae81267649a7ce53debe8196533f7a0472f5b.tar.bz2 llvm-b5eae81267649a7ce53debe8196533f7a0472f5b.tar.xz | |
[AArch64] Add the constraint to NEON scalar mla/mls instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193117 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/AArch64/AArch64InstrNEON.td | 36 |
1 files changed, 30 insertions, 6 deletions
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index 361909a398..9efbb0d34f 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -3246,6 +3246,21 @@ multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> { NoItinerary>; } +multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> { + let Constraints = "$Src = $Rd" in { + def shh : NeonI_Scalar3Diff<u, 0b01, opcode, + (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm), + !strconcat(asmop, " $Rd, $Rn, $Rm"), + [], + NoItinerary>; + def dss : NeonI_Scalar3Diff<u, 0b10, opcode, + (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm), + !strconcat(asmop, " $Rd, $Rn, $Rm"), + [], + NoItinerary>; + } +} + multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode, Instruction INSTH, Instruction INSTS> { @@ -3255,6 +3270,15 @@ multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode, (INSTS FPR32:$Rn, FPR32:$Rm)>; } +multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode, + Instruction INSTH, + Instruction INSTS> { + def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))), + (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>; + def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))), + (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>; +} + // Scalar Two Registers Miscellaneous multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode, @@ -3553,14 +3577,14 @@ defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>; defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>; // Signed Saturating Doubling Multiply-Add Long -defm SQDMLAL : NeonI_Scalar3Diff_HS_size<0b0, 0b1001, "sqdmlal">; -defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmlal, - SQDMLALshh, SQDMLALdss>; +defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">; +defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal, + SQDMLALshh, SQDMLALdss>; // Signed Saturating Doubling Multiply-Subtract Long -defm SQDMLSL : NeonI_Scalar3Diff_HS_size<0b0, 0b1011, "sqdmlsl">; -defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmlsl, - SQDMLSLshh, SQDMLSLdss>; +defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">; +defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl, + SQDMLSLshh, SQDMLSLdss>; // Signed Saturating Doubling Multiply Long defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">; |