diff options
| author | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-21 11:38:30 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2010-07-21 11:38:30 +0000 |
| commit | bc565014357a89c91a46a647714cb0d256186cc9 (patch) | |
| tree | 02717393829dea95fa216b0cc24b3a25bb927244 /lib | |
| parent | 50fb330b8da8dcde15717420dbbbab7d509d9fa1 (diff) | |
| download | llvm-bc565014357a89c91a46a647714cb0d256186cc9.tar.gz llvm-bc565014357a89c91a46a647714cb0d256186cc9.tar.bz2 llvm-bc565014357a89c91a46a647714cb0d256186cc9.tar.xz | |
Fix calling convention on ARM if vfp2+ is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109009 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 733042266d..5888c1bf38 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -831,8 +831,9 @@ static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCState &State, bool CanFail) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; + static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 }; - unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); + unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); if (Reg == 0) { // For the 2nd half of a v2f64, do not just fail. if (CanFail) @@ -850,6 +851,9 @@ static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, if (HiRegList[i] == Reg) break; + unsigned T = State.AllocateReg(LoRegList[i]); + assert(T == LoRegList[i] && "Could not allocate register"); + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], LocVT, LocInfo)); |