diff options
author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 14:41:52 +0000 |
---|---|---|
committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 14:41:52 +0000 |
commit | bd1958d8e99ebd5a885f848b2f688c399cfc9886 (patch) | |
tree | b6e601bf608dbf79bf81ad61465325d83ac3bd18 /lib | |
parent | f985f01574956da0d42e33d440deb63bf153d354 (diff) | |
download | llvm-bd1958d8e99ebd5a885f848b2f688c399cfc9886.tar.gz llvm-bd1958d8e99ebd5a885f848b2f688c399cfc9886.tar.bz2 llvm-bd1958d8e99ebd5a885f848b2f688c399cfc9886.tar.xz |
[SystemZ] Extend test-under-mask support to high GR32s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/SystemZ/SystemZInstrFormats.td | 5 | ||||
-rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.cpp | 8 | ||||
-rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 16 | ||||
-rw-r--r-- | lib/Target/SystemZ/SystemZPatterns.td | 6 |
4 files changed, 27 insertions, 8 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index b35aea8dfe..9ca1a8ad50 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -1386,6 +1386,11 @@ class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, let Constraints = "$R1 = $R1src"; } +// Like CompareRI, but expanded after RA depending on the choice of register. +class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls, + Immediate imm> + : Pseudo<(outs), (ins cls:$R1, imm:$I2), [(operator cls:$R1, imm:$I2)]>; + // Like StoreRXY, but expanded after RA depending on the choice of registers. class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls, bits<5> bytes, AddressingMode mode = bdxaddr20only> diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index f32cf9c527..2c48c78981 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -910,6 +910,14 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false); return true; + case SystemZ::TMLMux: + expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false); + return true; + + case SystemZ::TMHMux: + expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false); + return true; + case SystemZ::RISBMux: { bool DestIsHigh = isHighReg(MI->getOperand(0).getReg()); bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg()); diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 88508e33c5..340580af62 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1140,16 +1140,22 @@ let mayLoad = 1, Defs = [CC], Uses = [R0L] in // Test under mask. let Defs = [CC] in { + // TMxMux expands to TM[LH]x, depending on the choice of register. + def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, + Requires<[FeatureHighWord]>; + def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, + Requires<[FeatureHighWord]>; def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; - - def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>; - def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>; + def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; + def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; } -def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16>; -def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16>; +def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16, subreg_l32>; +def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16, subreg_l32>; +def : CompareGR64RI<TMHL, z_tm_reg, imm64hl16, subreg_h32>; +def : CompareGR64RI<TMHH, z_tm_reg, imm64hh16, subreg_h32>; //===----------------------------------------------------------------------===// // Prefetch diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td index af46919569..f3ca60b27a 100644 --- a/lib/Target/SystemZ/SystemZPatterns.td +++ b/lib/Target/SystemZ/SystemZPatterns.td @@ -113,11 +113,11 @@ multiclass CondStores64<Instruction insn, Instruction insninv, } // INSN performs a comparison between a 32-bit register and a constant. -// Record that it is equivalent to comparing the low word of a GR64 with IMM. +// Record that it is equivalent to comparing subreg SUBREG of a GR64 with IMM. class CompareGR64RI<Instruction insn, SDPatternOperator compare, - Immediate imm> + Immediate imm, SubRegIndex subreg> : Pat<(compare GR64:$R1, imm:$I2), - (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), + (insn (EXTRACT_SUBREG GR64:$R1, subreg), (imm.OperandTransform imm:$I2))>; // Try to use MVC instruction INSN for a load of type LOAD followed by a store |