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| author | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-04-30 16:00:49 +0000 |
|---|---|---|
| committer | Matheus Almeida <matheus.almeida@imgtec.com> | 2014-04-30 16:00:49 +0000 |
| commit | c3a5ef59e48a5fea5358cc6097d6cd2f99f61844 (patch) | |
| tree | 28159b9e9261b77866b2ac15bf45afa1fae63658 /lib | |
| parent | 3bdb9015b1226c33231794c1ace84cd5b8a7e6f3 (diff) | |
| download | llvm-c3a5ef59e48a5fea5358cc6097d6cd2f99f61844.tar.gz llvm-c3a5ef59e48a5fea5358cc6097d6cd2f99f61844.tar.bz2 llvm-c3a5ef59e48a5fea5358cc6097d6cd2f99f61844.tar.xz | |
[mips] Add instruction alias (dsll and dsrl).
Summary:
The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs.
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D3486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207664 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 7f895e23f9..1303028c68 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -440,6 +440,8 @@ def : InstAlias<"add $rs, $imm", def : InstAlias<"addu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; +def : InstAlias<"dsll $rd, $rt, $rs", + (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>; def : InstAlias<"dsubu $rt, $rs, $imm", (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, InvertedImOperand64: $imm),0>; @@ -449,6 +451,8 @@ def : InstAlias<"dsub $rs, $imm", def : InstAlias<"dsubu $rs, $imm", (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm), 0>; +def : InstAlias<"dsrl $rd, $rt, $rs", + (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>; /// Move between CPU and coprocessor registers let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { |