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author | Renato Golin <renato.golin@linaro.org> | 2014-03-26 12:52:28 +0000 |
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committer | Renato Golin <renato.golin@linaro.org> | 2014-03-26 12:52:28 +0000 |
commit | c4b058f9e7145765783fb741ea280acc4fea1f94 (patch) | |
tree | 9bf30fddda52ba7983b841347023b07a10592147 /lib | |
parent | 159e7f40956437a2513f54e19b03772bd3a0e942 (diff) | |
download | llvm-c4b058f9e7145765783fb741ea280acc4fea1f94.tar.gz llvm-c4b058f9e7145765783fb741ea280acc4fea1f94.tar.bz2 llvm-c4b058f9e7145765783fb741ea280acc4fea1f94.tar.xz |
Add @llvm.clear_cache builtin
Implementing the LLVM part of the call to __builtin___clear_cache
which translates into an intrinsic @llvm.clear_cache and is lowered
by each target, either to a call to __clear_cache or nothing at all
incase the caches are unified.
Updating LangRef and adding some tests for the implemented architectures.
Other archs will have to implement the method in case this builtin
has to be compiled for it, since the default behaviour is to bail
unimplemented.
A Clang patch is required for the builtin to be lowered into the
llvm intrinsic. This will be done next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204802 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.h | 5 | ||||
-rw-r--r-- | lib/Target/Mips/MipsISelLowering.h | 5 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 5 |
4 files changed, 17 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index bd80a503e2..639ff82ffd 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5386,6 +5386,8 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { (void)getControlRoot(); return 0; } + case Intrinsic::clear_cache: + return TLI->getClearCacheBuiltinName(); case Intrinsic::donothing: // ignore return 0; diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 022945f625..5f6ea75434 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -384,6 +384,11 @@ namespace llvm { bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override; + /// Clear cache library call + const char * getClearCacheBuiltinName() const { + return "__clear_cache"; + } + protected: std::pair<const TargetRegisterClass*, uint8_t> findRepresentativeClass(MVT VT) const override; diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 27492a8046..b03cccfb58 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -583,6 +583,11 @@ namespace llvm { bool MemcpyStrSrc, MachineFunction &MF) const; + /// Clear cache library call + const char * getClearCacheBuiltinName() const { + return "__clear_cache"; + } + /// isFPImmLegal - Returns true if the target can instruction select the /// specified FP immediate natively. If false, the legalizer will /// materialize the FP immediate as a load from a constant pool. diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 894cfc6d0c..ae13ca491c 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -770,6 +770,11 @@ namespace llvm { bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override; + /// Intel processors have a unified instruction and data cache + const char * getClearCacheBuiltinName() const { + return 0; // nothing to do, move along. + } + /// createFastISel - This method returns a target specific FastISel object, /// or null if the target does not support "fast" ISel. FastISel *createFastISel(FunctionLoweringInfo &funcInfo, |