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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:44:49 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:44:49 +0000 |
| commit | c669ad900d6a8f0c45f672828c023f857a249ba9 (patch) | |
| tree | 10577c916f59782a87b49a51d2a0fd35f18a04fb /lib | |
| parent | cb9ca905e358698f8732ec94a9aa8059beaa870b (diff) | |
| download | llvm-c669ad900d6a8f0c45f672828c023f857a249ba9.tar.gz llvm-c669ad900d6a8f0c45f672828c023f857a249ba9.tar.bz2 llvm-c669ad900d6a8f0c45f672828c023f857a249ba9.tar.xz | |
[ARM64] Properly support both apple and standard syntax for FMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205896 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM64/ARM64InstrFormats.td | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/lib/Target/ARM64/ARM64InstrFormats.td b/lib/Target/ARM64/ARM64InstrFormats.td index af8b683821..378b698909 100644 --- a/lib/Target/ARM64/ARM64InstrFormats.td +++ b/lib/Target/ARM64/ARM64InstrFormats.td @@ -3277,8 +3277,10 @@ class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode, let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode, - RegisterClass srcType, RegisterOperand dstType, string asm> - : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd[1], $Rn", "", []>, + RegisterClass srcType, RegisterOperand dstType, string asm, + string kind> + : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, + "{\t$Rd"#kind#"[1], $Rn|"#kind#"\t$Rd[1], $Rn}", "", []>, Sched<[WriteFCopy]> { bits<5> Rd; bits<5> Rn; @@ -3293,8 +3295,10 @@ class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode, let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode, - RegisterOperand srcType, RegisterClass dstType, string asm> - : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn[1]", "", []>, + RegisterOperand srcType, RegisterClass dstType, string asm, + string kind> + : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, + "{\t$Rd, $Rn"#kind#"[1]|"#kind#"\t$Rd, $Rn[1]}", "", []>, Sched<[WriteFCopy]> { bits<5> Rd; bits<5> Rn; @@ -3331,21 +3335,16 @@ multiclass UnscaledConversion<string asm> { } def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128, - asm#".d"> { + asm, ".d"> { let Inst{31} = 1; let Inst{22} = 0; } def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64, - asm#".d"> { + asm, ".d"> { let Inst{31} = 1; let Inst{22} = 0; } - - def : InstAlias<asm#"$Vd.d[1], $Rn", - (!cast<Instruction>(NAME#XDHighr) V128:$Vd, GPR64:$Rn), 0>; - def : InstAlias<asm#"$Rd, $Vn.d[1]", - (!cast<Instruction>(NAME#DXHighr) GPR64:$Rd, V128:$Vn), 0>; } //--- |