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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-14 19:47:47 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-14 19:47:47 +0000 |
| commit | c83d504085c17697f2a24d0a9fbad4503105ec41 (patch) | |
| tree | 580ebeda771a09098a3835e9d8228365ca58cc40 /lib | |
| parent | 64090bd2d468ec70b9644bdf492684dd278de8a7 (diff) | |
| download | llvm-c83d504085c17697f2a24d0a9fbad4503105ec41.tar.gz llvm-c83d504085c17697f2a24d0a9fbad4503105ec41.tar.bz2 llvm-c83d504085c17697f2a24d0a9fbad4503105ec41.tar.xz | |
Reorganize ARM assembler aliases.
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135179 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 33 |
1 files changed, 19 insertions, 14 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 445ef6cd21..b6df3ba110 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1629,7 +1629,6 @@ def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", let Inst{23-0} = svc; } } -def : MnemonicAlias<"swi", "svc">; // Store Return State is a system instruction -- for disassembly only let isCodeGenOnly = 1 in { // FIXME: This should not use submode! @@ -2053,13 +2052,6 @@ defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>; } // neverHasSideEffects -// Load / Store Multiple Mnemonic Aliases -def : MnemonicAlias<"ldmfd", "ldm">; -def : MnemonicAlias<"ldmia", "ldm">; -def : MnemonicAlias<"stmfd", "stmdb">; -def : MnemonicAlias<"stmia", "stm">; -def : MnemonicAlias<"stmea", "stm">; - // FIXME: remove when we have a way to marking a MI with these properties. // FIXME: Should pc be an implicit operand like PICADD, etc? let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, @@ -3307,8 +3299,6 @@ def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, } } -def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; - def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, "dsb", "\t$opt", []>, Requires<[IsARM, HasDB]> { @@ -3317,8 +3307,6 @@ def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, let Inst{3-0} = opt; } -def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; - // ISB has only full system option def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, "isb", "\t$opt", []>, @@ -3328,8 +3316,6 @@ def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, let Inst{3-0} = opt; } -def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; - let usesCustomInserter = 1 in { let Uses = [CPSR] in { def ATOMIC_LOAD_ADD_I8 : PseudoInst< @@ -4064,3 +4050,22 @@ include "ARMInstrVFP.td" include "ARMInstrNEON.td" +//===----------------------------------------------------------------------===// +// Assembler aliases +// + +// Memory barriers +def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>; +def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>; +def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>; + +// System instructions +def : MnemonicAlias<"swi", "svc">; + +// Load / Store Multiple +def : MnemonicAlias<"ldmfd", "ldm">; +def : MnemonicAlias<"ldmia", "ldm">; +def : MnemonicAlias<"stmfd", "stmdb">; +def : MnemonicAlias<"stmia", "stm">; +def : MnemonicAlias<"stmea", "stm">; + |