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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-14 21:26:42 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-14 21:26:42 +0000 |
| commit | c8ae39e746a20dc326def0ccfc052df3e21f16d3 (patch) | |
| tree | 4beedc52b6ada45c792c3323ae6a0b65513eb759 /lib | |
| parent | f54645346664e07a222281e51bad36b259a0d0af (diff) | |
| download | llvm-c8ae39e746a20dc326def0ccfc052df3e21f16d3.tar.gz llvm-c8ae39e746a20dc326def0ccfc052df3e21f16d3.tar.bz2 llvm-c8ae39e746a20dc326def0ccfc052df3e21f16d3.tar.xz | |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 28c0318e02..c1489b9905 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3701,7 +3701,7 @@ def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, class MovRRCopro<string opc, bit direction, list<dag> pattern = [/* For disassembly only */]> - : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, + : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { let Inst{23-21} = 0b010; @@ -3727,7 +3727,7 @@ def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; class MovRRCopro2<string opc, bit direction, list<dag> pattern = [/* For disassembly only */]> - : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, + : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { let Inst{31-28} = 0b1111; diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index b68314a7eb..c2c6cbcac0 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3355,7 +3355,7 @@ class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, class t2MovRRCopro<bits<4> Op, string opc, bit direction, list<dag> pattern = []> : T2Cop<Op, (outs), - (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), + (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { let Inst{27-24} = 0b1100; let Inst{23-21} = 0b010; |