R600: Fix the fetch limits for R600 generation GPUs

Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183560 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 30 insertions, 27 deletions

diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
index 335b26cbf2..099a491847 100644
--- a/lib/Target/R600/AMDGPU.td
+++ b/lib/Target/R600/AMDGPU.td
@@ -75,7 +75,16 @@ def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
         "true",
         "Specify use of dedicated vertex cache.">;
 
+class SubtargetFeatureFetchLimit <string Value> :
+                          SubtargetFeature <"fetch"#Value,
+        "TexVTXClauseSize",
+        Value,
+        "Limit the maximum number of fetches in a clause to "#Value>;
 
+def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
+def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
+
+//===----------------------------------------------------------------------===//
 
 def AMDGPUInstrInfo : InstrInfo {
   let guessInstructionProperties = 1;
diff --git a/lib/Target/R600/AMDGPUSubtarget.cpp b/lib/Target/R600/AMDGPUSubtarget.cpp
index da342892da..158903020f 100644
--- a/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -34,19 +34,10 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
   DefaultSize[1] = 1;
   DefaultSize[2] = 1;
   HasVertexCache = false;
+  TexVTXClauseSize = 0;
   ParseSubtargetFeatures(GPU, FS);
   DevName = GPU;
   Device = AMDGPUDeviceInfo::getDeviceFromName(DevName, this, Is64bit);
-
-  // FIXME: The code in the comment below was the original code. But the
-  // condition is always true, generating a warning when compiled with
-  // gcc. Vincent Lejeune indicated in a mail to llvm-commits 2013-05-23 that he
-  // will look into this. The code 'TexVTXClauseSize = 16' is just a temporary
-  // equivalent replacement, to get rid of the compiler warning.
-
-  // TexVTXClauseSize = (Device->getGeneration() >= AMDGPUDeviceInfo::HD4XXX)?16:8;
-
-  TexVTXClauseSize = 16;
 }
 
 AMDGPUSubtarget::~AMDGPUSubtarget() {
diff --git a/lib/Target/R600/AMDILDeviceInfo.h b/lib/Target/R600/AMDILDeviceInfo.h
index 4b2c3a53c7..04530e6110 100644
--- a/lib/Target/R600/AMDILDeviceInfo.h
+++ b/lib/Target/R600/AMDILDeviceInfo.h
@@ -71,7 +71,8 @@ namespace llvm {
     /// These have to be in order with the older generations
     /// having the lower number enumerations.
     enum Generation {
-      HD4XXX = 0, ///< 7XX based devices.
+      HD3XXX = 0, ///< 6XX based devices.
+      HD4XXX, ///< 7XX based devices.
       HD5XXX, ///< Evergreen based devices.
       HD6XXX, ///< NI/Evergreen+ based devices.
       HD7XXX, ///< Southern Islands based devices.
diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td
index 0cbe919d81..4c377d05b9 100644
--- a/lib/Target/R600/Processors.td
+++ b/lib/Target/R600/Processors.td
@@ -10,37 +10,39 @@
 class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
 : Processor<Name, itin, Features>;
 def : Proc<"",           R600_VLIW5_Itin,
-    [FeatureR600ALUInst, FeatureVertexCache]>;
+    [FeatureR600ALUInst, FeatureVertexCache, FeatureFetchLimit8]>;
 def : Proc<"r600",       R600_VLIW5_Itin,
-    [FeatureR600ALUInst , FeatureVertexCache]>;
+    [FeatureR600ALUInst , FeatureVertexCache, FeatureFetchLimit8]>;
 def : Proc<"rs880",      R600_VLIW5_Itin,
-    [FeatureR600ALUInst]>;
+    [FeatureR600ALUInst, FeatureFetchLimit8]>;
 def : Proc<"rv670",      R600_VLIW5_Itin,
-    [FeatureR600ALUInst, FeatureFP64, FeatureVertexCache]>;
+    [FeatureR600ALUInst, FeatureFP64, FeatureVertexCache, FeatureFetchLimit8]>;
 def : Proc<"rv710",      R600_VLIW5_Itin,
-    [FeatureVertexCache]>;
+    [FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"rv730",      R600_VLIW5_Itin,
-    [FeatureVertexCache]>;
+    [FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"rv770",      R600_VLIW5_Itin,
-    [FeatureFP64, FeatureVertexCache]>;
+    [FeatureFP64, FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"cedar",      R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
+    [FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"redwood",    R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
+    [FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"sumo",       R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages]>;
+    [FeatureByteAddress, FeatureImages, FeatureFetchLimit16]>;
 def : Proc<"juniper",    R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
+    [FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"cypress",    R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache]>;
+    [FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"barts",      R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
+    [FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"turks",      R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages, FeatureVertexCache]>;
+    [FeatureByteAddress, FeatureImages, FeatureVertexCache, FeatureFetchLimit16]>;
 def : Proc<"caicos",     R600_VLIW5_Itin,
-    [FeatureByteAddress, FeatureImages]>;
+    [FeatureByteAddress, FeatureImages, FeatureFetchLimit16]>;
 def : Proc<"cayman",     R600_VLIW4_Itin,
-    [FeatureByteAddress, FeatureImages, FeatureFP64]>;def : Proc<"SI",         SI_Itin, [Feature64BitPtr, FeatureFP64]>;
+    [FeatureByteAddress, FeatureImages, FeatureFP64, FeatureFetchLimit16]>;
+
+def : Proc<"SI",         SI_Itin, [Feature64BitPtr, FeatureFP64]>;
 def : Proc<"tahiti",     SI_Itin, [Feature64BitPtr, FeatureFP64]>;
 def : Proc<"pitcairn",   SI_Itin, [Feature64BitPtr, FeatureFP64]>;
 def : Proc<"verde",      SI_Itin, [Feature64BitPtr, FeatureFP64]>;