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author | Chris Lattner <sabre@nondot.org> | 2008-03-07 06:36:32 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2008-03-07 06:36:32 +0000 |
commit | d1108222fd7b49d660fa63868cd2428fa1d49c17 (patch) | |
tree | 0830e6b4e68d92245e7d4a29d4973fc57ddb99c1 /lib | |
parent | 65bc1220459aef4a7a1bd57cdc0f0113d4250469 (diff) | |
download | llvm-d1108222fd7b49d660fa63868cd2428fa1d49c17.tar.gz llvm-d1108222fd7b49d660fa63868cd2428fa1d49c17.tar.bz2 llvm-d1108222fd7b49d660fa63868cd2428fa1d49c17.tar.xz |
mark frem as expand for all legal fp types on x86, regardless of whether
we're using SSE or not. This fixes PR2122.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48006 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d0d3f64458..22ddd83295 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -215,7 +215,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); + setOperationAction(ISD::FREM , MVT::f32 , Expand); setOperationAction(ISD::FREM , MVT::f64 , Expand); + setOperationAction(ISD::FREM , MVT::f80 , Expand); setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); setOperationAction(ISD::CTPOP , MVT::i8 , Expand); @@ -358,10 +360,8 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) // We don't support sin/cos/fmod setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FREM , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); // Expand FP immediates into loads from the stack, except for the special // cases we handle. @@ -398,7 +398,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) // We don't support sin/cos/fmod setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); // Special cases we handle for FP constants. addLegalFPImmediate(APFloat(+0.0f)); // xorps |