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authorMisha Brukman <brukman+llvm@gmail.com>2003-06-05 23:30:27 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2003-06-05 23:30:27 +0000
commitd4ad1d10bc496d1dc1e47d2a80a6e09f4547bc4f (patch)
treef619fd47031e622e98d7d3710679b2ce11c5d936 /lib
parent3d194ac26bd61968ac9ed8de5bde42e902724d19 (diff)
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Do not preset the cc register, the instructions actually use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6637 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/SparcV9/SparcV9.td37
1 files changed, 17 insertions, 20 deletions
diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td
index 6c3aa567df..1d9c4b8fe8 100644
--- a/lib/Target/SparcV9/SparcV9.td
+++ b/lib/Target/SparcV9/SparcV9.td
@@ -77,27 +77,24 @@ set isDeprecated = 1 in {
}
#endif
-// These instructions are hacked to really represent A.5 instructions,
-// but with cc hardcoded to be %fcc0. Hence, they behave like FBPfcc instrs.
+// We now make these same opcodes represent the FBPfcc instructions
set op2 = 0b101 in {
- set cc = 0b00 in {
- def FBA : F2_3<0b1000, "fba">; // Branch always
- def FBN : F2_3<0b0000, "fbn">; // Branch never
- def FBU : F2_3<0b0111, "fbu">; // Branch on unordered
- def FBG : F2_3<0b0110, "fbg">; // Branch >
- def FBUG : F2_3<0b0101, "fbug">; // Branch on unordered or >
- def FBL : F2_3<0b0100, "fbl">; // Branch <
- def FBUL : F2_3<0b0011, "fbul">; // Branch on unordered or <
- def FBLG : F2_3<0b0010, "fblg">; // Branch < or >
- def FBNE : F2_3<0b0001, "fbne">; // Branch !=
- def FBE : F2_3<0b1001, "fbe">; // Branch ==
- def FBUE : F2_3<0b1010, "fbue">; // Branch on unordered or ==
- def FBGE : F2_3<0b1011, "fbge">; // Branch > or ==
- def FBUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or ==
- def FBLE : F2_3<0b1101, "fble">; // Branch < or ==
- def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
- def FBO : F2_3<0b1111, "fbo">; // Branch on ordered
- }
+ def FBA : F2_3<0b1000, "fba">; // Branch always
+ def FBN : F2_3<0b0000, "fbn">; // Branch never
+ def FBU : F2_3<0b0111, "fbu">; // Branch on unordered
+ def FBG : F2_3<0b0110, "fbg">; // Branch >
+ def FBUG : F2_3<0b0101, "fbug">; // Branch on unordered or >
+ def FBL : F2_3<0b0100, "fbl">; // Branch <
+ def FBUL : F2_3<0b0011, "fbul">; // Branch on unordered or <
+ def FBLG : F2_3<0b0010, "fblg">; // Branch < or >
+ def FBNE : F2_3<0b0001, "fbne">; // Branch !=
+ def FBE : F2_3<0b1001, "fbe">; // Branch ==
+ def FBUE : F2_3<0b1010, "fbue">; // Branch on unordered or ==
+ def FBGE : F2_3<0b1011, "fbge">; // Branch > or ==
+ def FBUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or ==
+ def FBLE : F2_3<0b1101, "fble">; // Branch < or ==
+ def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
+ def FBO : F2_3<0b1111, "fbo">; // Branch on ordered
}
// Section A.5: Branch on FP condition codes with prediction - p143